Datasheet > P520-00DC

P520-00DC

更新时间： 2024-09-30 09:56:03

品牌	Logo	应用领域
PLL		石英晶振压控振荡器
页数	文件大小	规格书
8页	218K
描述
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

P520-00DC 数据手册

PLL520-00

Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)

FEATURES

DIE CONFIGURATION

65 mil

•

100MHz to 200MHz Fundamental Mode Crystal.

Output range: 100 – 200MHz (no multiplication),

200 – 400MHz (2x multiplier), 400 – 700MHz (4x

multiplier), or 800MHz – 1GHz (LVDS output

only for 8x multiplier).

(1550,1475)

24 23 22 21

GNDBUF

XIN

CMOS

LVDSB

PECLB

•

Available outputs: PECL, LVDS, or CMOS (High

Drive (30mA) or Standard Drive (10mA) output).

Selectable OE Logic (enable high or enable low).

Integrated variable capacitors.

Supports 3.3V-Power Supply.

Available in die form.

Die ID:

A1919-19A

XOUT

SEL3^

•

VDDBUF

SEL2^

Thickness 10 mil.

PECL

DESCRIPTION

CTRL

LVDS

C502A

PLL520-00 is a VCXO IC specifically designed to

pull high frequency fundamental crystals. Its design

was optimized to tolerate higher limits of

VCON

OE_SEL^

(0,0)

interelectrodes capacitance and bonding

capacitance to improve yield. It achieves very low

current into the crystal resulting in better overall

stability. Its internal varicaps allow an on chip

frequency pulling, controlled by the VCON input.

Note: ^ denotes internal pull up

OUTPUT SELECTION AND ENABLE

BLOCK DIAGRAM

OUTSEL1

(Pad #18)

OUTSEL0

(Pad #25)

Selected Output

SEL

High Drive CMOS

Standard CMOS

LVDS

PLL

PECL (default)

Oscillator

Amplifier

(Phase

Locked

Loop)

VCON

OE_SELECT

(Pad #9)

OE_CTRL

(Pad #30)

XIN

State

integrated

varicaps

Tri-state

XOUT

1 (Default) Output enabled

0 (Default) Output enabled

PLL by-pass

PLL520-00

1 (Default)

Tri-state

Pad #9, 18, 25: Bond to GND to set to “0”. No connection results to

“default” setting through internal pull-up.

DIE SPECIFICATIONS

Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9)

is “1”

Name

Size

Value

Logical states defined by CMOS levels if OE_SELECT is “0

65 x 62 mil

GND

Reverse side

Pad dimensions

Thickness

80 micron x 80 micron

10 mil

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1

12 3 4 5 6 7 8

中文翻译

下载PDF

与P520-00DC相关器件

型号	品牌	获取价格	描述	数据表
P520-05OC	PLL	获取价格	Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
P520-05QC	PLL	获取价格	Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
P520-06QC	PLL	获取价格	Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
P520-07OC	PLL	获取价格	Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
P520-08OC	PLL	获取价格	Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
P520-08QC	PLL	获取价格	Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
P520-09OC	PLL	获取价格	Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
P520-09QC	PLL	获取价格	Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
P5-200-NP	SUMIDA	获取价格	IFT COILS
P5200TR	ETAL	获取价格	Digital Isolation Transformer

与P520-00DC相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

30
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

27
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

26
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

35

产品中心

服务支持

精选活动

关于我们

帮助中心

P520-00DC

P520-00DC 数据手册

与P520-00DC相关器件

与P520-00DC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

P520-00DC

P520-00DC 数据手册

与P520-00DC相关器件

与P520-00DC相关文章

您还可以找

您在本页遇到什么问题？