Datasheet > P520-07OC

P520-07OC

更新时间： 2024-09-30 02:51:15

品牌	Logo	应用领域
PLL		石英晶振压控振荡器
页数	文件大小	规格书
8页	240K
描述
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)

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数据手册

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P520-07OC 数据手册

PLL520-05/-06/-07/-08/-09

Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)

FEATURES

PIN CONFIGURATION

(Top View)

•

100MHz to 200MHz Fundamental Mode Crystal.

Output range: 100 – 200MHz (no multiplication),

200 – 400MHz (2x multiplier), 400 – 800MHz (4x

multiplier), or 800MHz – 1GHz (PLL520-09

TSSOP only, 8x multiplier).

VDD

XIN

SEL0^

SEL1^

GND

XOUT

SEL3^

SEL2^

•

High yield design supports up to 2pF stray

capacitance at 200MHz.

CMOS (Standard drive PLL520-07 or Selectable

Drive PLL520-06), PECL (Enable low PLL520-08

or Enable high PLL520-05) or LVDS output

(PLL520-09).

CLKC

VDD

CLKT

GND

VCON

GND

•

Integrated variable capacitors.

Supports 3.3V-Power Supply.

Available in 16-Pin (TSSOP or 3x3mm QFN)

Note: PLL520-06 only available in 3x3mm.

Note: PLL520-07 only available in TSSOP.

GND

DESCRIPTION

The PLL520-05/-06/-07/-08/-09 is a family of VCXO

ICs specifically designed to pull high frequency

fundamental crystals. Their design was optimized to

tolerate higher limits of interelectrode capacitance

and bonding capacitance to improve yield. They

achieve very low current into the crystal resulting in

better overall stability. Their internal varicaps allow

an on chip frequency pulling, controlled by the

VCON input.

12 11 10

XIN

XOUT

SEL2^

GND

CLKC

VDD

P520-0x

CLKT

^: Internal pull-up

*: PLL520-06 pin 12 is output drive select (DRIVSEL)

(0 for High Drive CMOS, 1 for Standard Drive CMOS)

BLOCK DIAGRAM

SEL

OUTPUT ENABLE LOGICAL LEVELS

State

Part #

PLL

0 (Default) Output enabled

PLL520-08

Oscillator

Amplifier

(Phase

Locked

Loop)

VCON

Tri-state

PLL520-05

PLL520-06

PLL520-07

PLL520-09

XIN

integrated

varicaps

1 (Default) Output enabled

XOUT

PLL by-pass

OE input: Logical states defined by PECL levels for PLL520-08

Logical states defined by CMOS levels for PLL520-05/-06/-

07/-09

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1

12 3 4 5 6 7 8

中文翻译

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P520-09OC	PLL	获取价格	Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
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P520-17SC	PLL	获取价格	Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)