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P520-10DC PDF预览

P520-10DC

更新时间: 2024-09-30 03:43:47
品牌 Logo 应用领域
PLL 石英晶振压控振荡器
页数 文件大小 规格书
8页 242K
描述
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)

P520-10DC 数据手册

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PLL520-10  
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)  
FEATURES  
DIE CONFIGURATION  
65 mil  
65MHz to 130MHz Fundamental Mode Crystal.  
Output range: 65MHz – 800MHz (selectable 1x,  
2x, 4x and 8x multipliers).  
(1550,1475)  
25  
24 23 22 21  
20  
19  
18  
17  
Low Injection Power for crystal 50uW.  
Available outputs: PECL, LVDS, or CMOS (High  
Drive (30mA) or Standard Drive (10mA) output).  
Integrated variable capacitors.  
Supports 3.3V-Power Supply.  
Available in die form.  
GNDBUF  
16  
15  
14  
26  
XIN  
CMOS  
LVDSB  
PECLB  
Die ID:  
A1313-13A  
27  
28  
XOUT  
SEL3^  
Thickness 10 mil.  
13  
12  
VDDBUF  
VDDBUF  
SEL2^  
29  
11  
DESCRIPTION  
PECL  
OE  
30  
31  
CTRL  
10  
9
LVDS  
C502A  
PLL520-10 is a VCXO IC specifically designed to  
pull frequency fundamental crystals from 65MHz to  
130MHz, with an integrated Phase Locked Loop for  
selectable 1x (no PLL), 2x, 4x or 8x multipliers. Its  
design was optimized to tolerate higher limits of  
interelectrode capacitance and bonding capacitance  
to improve yield. It achieves very low current into the  
crystal resulting in better overall stability. Its internal  
varicaps allow an on chip frequency pulling,  
controlled by the VCON input.  
VCON  
OE_SEL^  
2
4
5
6
8
1
3
7
(0,0)  
Y
X
DIE SPECIFICATIONS  
Name  
Value  
Size  
62 x 65 mil  
GND  
Reverse side  
BLOCK DIAGRAM  
Pad dimensions  
Thickness  
80 micron x 80 micron  
10 mil  
SEL  
OUTPUT SELECTION AND ENABLE  
OE  
Q
OUTSEL1  
(Pad #18)  
OUTSEL0  
PLL  
Selected Output  
(Pad #25)  
Oscillator  
Amplifier  
w/  
(Phase  
Locked  
Loop)  
VCON  
0
0
1
1
0
1
0
1
High Drive CMOS  
Standard CMOS  
LVDS  
Q
X+  
X-  
integrated  
varicaps  
PECL (default)  
PLL by-pass  
PLL520-10  
OE_SELECT  
(Pad #9)  
OE_CTRL  
(Pad #30)  
State  
0
Tri-state  
0
1 (Default) Output enabled  
0 (Default) Output enabled  
1 (Default)  
1
Tri-state  
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”  
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad  
#9) is “1”  
Logical states defined by CMOS levels if OE_SELECT is “0”  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1  

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