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P4C168L-25DMB PDF预览

P4C168L-25DMB

更新时间: 2024-11-26 20:06:27
品牌 Logo 应用领域
PYRAMID 静态存储器内存集成电路
页数 文件大小 规格书
14页 628K
描述
Standard SRAM, 4KX4, 25ns, CMOS, CDIP20, 0.300 INCH, CERAMCI, DIP-20

P4C168L-25DMB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:20
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.5
最长访问时间:25 nsJESD-30 代码:R-CDIP-T20
JESD-609代码:e0内存密度:16384 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
功能数量:1端子数量:20
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:4KX4
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified筛选级别:MIL-STD-883 Class B
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

P4C168L-25DMB 数据手册

 浏览型号P4C168L-25DMB的Datasheet PDF文件第2页浏览型号P4C168L-25DMB的Datasheet PDF文件第3页浏览型号P4C168L-25DMB的Datasheet PDF文件第4页浏览型号P4C168L-25DMB的Datasheet PDF文件第5页浏览型号P4C168L-25DMB的Datasheet PDF文件第6页浏览型号P4C168L-25DMB的Datasheet PDF文件第7页 
P4C168/P4C168L , P4C169, P4C170  
ULTRA HIGH SPEED 4K x 4  
STATIC CMOS RAMS  
FEATURES  
Full CMOS, 6T Cell  
Three Options  
– P4C168 Low Power Standby Mode  
– P4C169 Fast Chip Select Control  
– P4C170 Fast Chip Select, Output Enable  
Controls  
High Speed (Equal Access and Cycle Times)  
– 12/15/20/25/35ns (Commercial)  
– 20/25/35/45/55/70ns (P4C168 Military)  
Low Power Operation (Commercial)  
– 715 mW Active  
– 193 mW Standby (TTL Input) P4C168  
– 83 mW Standby (CMOS Input) P4C168  
Standard Pinout (JEDEC Approved)  
– P4C168: 20-pin DIP, SOJ, LCC, SOIC,  
CERPACK, and Flat Pack  
– P4C169: 20-pin DIP and SOIC  
– P4C170: 22-pin DIP  
Single 5V±10% Power Supply  
Fully TTL Compatible, Common I/O Ports  
DESCRIPTION  
The P4C168, P4C169 and P4C170 are a family of  
16,384-bit ultra high-speed static RAMs organized as  
4K x 4. All three devices have common input/output  
ports.The P4C168 enters the standby mode when the  
chip enable (CE) control goes HIGH; with CMOS input  
levels, power consumption is only 83mW in this mode.  
Both the P4C169 and the P4C170 offer a fast chip select  
access time that is only 67% of the address access time.  
In addition, the P4C170 includes an output enable (OE)  
controltoeliminatedatabuscontention.TheRAMsoper-  
ate from a single 5V ± 10% tolerance power supply.  
Access times as fast as 12 nanoseconds are available,  
permitting greatly enhanced system operating speeds.  
CMOS is used to reduce power consumption to a low  
715 mW active, 193 mW standby.  
TheP4C168andP4C169areavailablein20-pin(P4C170  
in 22-pin) 300 mil DIP packages providing excellent  
board level densities. The P4C168 is also available in  
20-pin 300 mil SOIC, SOJ, CERPACK, and Flat Pack  
packages.  
The P4C169 is also available in a 20-pin 300 mil SOIC  
package.  
PIN CONFIGURATIONS  
FUNCTIONAL BLOCK DIAGRAM  
P4C170  
DIP (P3)  
P4C168  
DIP (P2, C6, D2)  
SOIC (S2)  
P4C169  
DIP (P2)  
SOIC (S2)  
SOJ (J2)  
CERPACK (F2)  
SOLDER SEAL FLAT PACK (FS-2)  
Document # SRAM107 REV E  
Revised March 2010  
1

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