Datasheet > 存储 > SRAM> P4C164L-80P6ILF

P4C164L-80P6ILF

更新时间： 2025-07-15 03:06:07

品牌	Logo	应用领域
PYRAMID		/
页数	文件大小	规格书
11页	112K
描述
LOW POWER 8K x 8 STATIC CMOS RAM

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中文翻译

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数据手册

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P4C164L-80P6ILF 数据手册

P4C164L

LOW POWER 8K x 8

STATIC CMOS RAM

FEATURES

Common Data I/O

Three-State Outputs

V_CCCurrent (Commercial/Industrial)

— Operating: 55 mA

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

—28-Pin 300 and 600 mil DIP

—28-Pin 330 mil SOP

— CMOS Standby: 3 µA

Access Times

—80/100 (Commercial or Industrial)

Single 5 Volts ±10% Power Supply

Easy Memory Expansion Using CE₁,CE₂and OE

Inputs

DESCRIPTION

The P4C164L is a 64K density low power CMOS

static RAM organized as 8Kx8. The CMOS memory

requires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Memory locations are specified on address pins A₀to

A₁₂. Reading is accomplished by device selection (CE₁

low CE₂high) and output enabling (OE) while write en-

able (WE) remains HIGH. By presenting the address

under these conditions, the data in the addressed memory

location is presented on the data input/output pins. The

input/output pins stay in the HIGH Z state when either

CE₁or OE is HIGH or WE or CE₂is LOW.

Access times of 80 ns and 100 ns are available. CMOS

is utilized to reduce power consumption to a low level.

Package options for the P4C164L include 28-pin 300 and

600 mil DIP and 28-pin 330 mil SOP packages.

The P4C164L device provides asynchronous operation

with matching access and cycle times.

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM

DIP (P5, P6), SOP (S5)

TOP VIEW

Document # SRAM116 REV B

Revised June 2007

12 3 4 5 6 7...11

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与P4C164L-80P6ILF相关器件

型号	品牌	获取价格	描述	数据表
P4C164L-80SC	PYRAMID	获取价格	Standard SRAM, 8KX8, 80ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, SOIC-28
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