Datasheet > P130-09SC

P130-09SC

更新时间： 2024-11-18 09:54:07

品牌	Logo	应用领域
PLL		/
页数	文件大小	规格书
5页	236K
描述
High Speed Translator Buffer to LVDS

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数据手册

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P130-09SC 数据手册

PLL130-09

High Speed Translator Buffer to LVDS

FEATURES

PIN CONFIGURATION

(TOP VIEW)

•

Differential LVDS output

Single AC coupled input (min. 100mV swing).

Input range from DC to 1.0 GHz.

2.5V to 3.3V operation.

GND

REF_IN

GND

VDD

Available in 8-Pin SOIC or 3x3mm QFN.

GND

LVDS_BAR

VDD

DESCRIPTION

LVDS

The PLL130-09 is a low cost, high performance,

high speed, buffer that reproduces any input fre-

quency from DC to 1.0GHz. It provides a pair of

differential LVDS output. Any input signal with at

least 100mV swing can be used as reference

signal. This chip is ideal for conversion from sine

wave, TTL, CMOS, or PECL to LVDS.

GND

LVDS_BAR

VDD

¹⁴PLL130-09

GND

LVDS

GND

OE^

Note: ^ denotes internal pull up

BLOCK DIAGRAM

LVDS_BAR

LVDS

Input

Amplifier

REF_IN

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

12 3 4 5

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