OXCF950 rev B DATA SHEET V 1.0
OXFORD SEMICONDUCTOR LTD.
6.4.1
6.5
6.5.1
FIFO CONTROL REGISTER ‘FCR’................................................................................................................................ 36
LINE CONTROL & STATUS............................................................................................................................................... 37
FALSE START BIT DETECTION .................................................................................................................................... 37
6.5.2
6.5.3
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.7
LINE CONTROL REGISTER ‘LCR’ ................................................................................................................................ 37
LINE STATUS REGISTER ‘LSR’.................................................................................................................................... 37
INTERRUPTS & SLEEP MODE ......................................................................................................................................... 39
INTERRUPT ENABLE REGISTER ‘IER’ ........................................................................................................................ 39
INTERRUPT STATUS REGISTER ‘ISR’ ........................................................................................................................ 40
INTERRUPT DESCRIPTION .......................................................................................................................................... 40
SLEEP MODE ................................................................................................................................................................. 41
MODEM INTERFACE......................................................................................................................................................... 41
MODEM CONTROL REGISTER ‘MCR’.......................................................................................................................... 41
MODEM STATUS REGISTER ‘MSR’............................................................................................................................. 42
6.7.1
6.7.2
6.8
OTHER STANDARD REGISTERS ..................................................................................................................................... 42
DIVISOR LATCH REGISTERS ‘DLL & DLM’ ................................................................................................................. 42
SCRATCH PAD REGISTER ‘SPR’................................................................................................................................. 42
AUTOMATIC FLOW CONTROL......................................................................................................................................... 42
ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................... 42
SPECIAL CHARACTER DETECTION............................................................................................................................ 43
AUTOMATIC IN-BAND FLOW CONTROL ..................................................................................................................... 44
6.8.1
6.8.2
6.9
6.9.1
6.9.2
6.9.3
6.9.4
AUTOMATIC OUT-OF-BAND FLOW CONTROL........................................................................................................... 44
6.10 BAUD RATE GENERATION............................................................................................................................................... 44
6.10.1
6.10.2
6.10.3
6.10.4
GENERAL OPERATION ................................................................................................................................................. 44
CLOCK PRESCALER REGISTER ‘CPR’ ....................................................................................................................... 45
TIMES CLOCK REGISTER ‘TCR’................................................................................................................................... 45
INPUT CLOCK OPTIONS ............................................................................................................................................... 46
6.10.5
6.10.6
6.10.7
TTL CLOCK MODULE .................................................................................................................................................... 47
EXTERNAL 1X CLOCK MODE....................................................................................................................................... 47
CRYSTAL OSCILLATOR CIRCUIT ................................................................................................................................ 47
6.11 ADDITIONAL FEATURES .................................................................................................................................................. 47
6.11.1
6.11.2
6.11.3
6.11.4
6.11.5
6.11.6
ADDITIONAL STATUS REGISTER ‘ASR’...................................................................................................................... 47
FIFO FILL LEVELS ‘TFL & RFL’..................................................................................................................................... 48
ADDITIONAL CONTROL REGISTER ‘ACR’.................................................................................................................. 48
TRANSMITTER TRIGGER LEVEL ‘TTL’ ........................................................................................................................ 49
RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ........................................................................................................ 49
FLOW CONTROL LEVELS ‘FCL & FCH’ ....................................................................................................................... 49
6.11.7
6.11.8
6.11.9
DEVICE IDENTIFICATION REGISTERS ....................................................................................................................... 50
CLOCK SELECT REGISTER ‘CKS’ ............................................................................................................................... 50
NINE-BIT MODE REGISTER ‘NMR’............................................................................................................................... 50
6.11.10 MODEM DISABLE MASK ‘MDM’ .................................................................................................................................... 51
6.11.11 READABLE FCR ‘RFC’................................................................................................................................................... 52
6.11.12 GOOD-DATA STATUS REGISTER ‘GDS’ ..................................................................................................................... 52
6.11.13 DMA STATUS REGISTER ‘DMS’................................................................................................................................... 52
6.11.14 PORT INDEX REGISTER ‘PIX’ ....................................................................................................................................... 52
6.11.15 CLOCK ALTERATION REGISTER ‘CKA’....................................................................................................................... 52
6.11.16 MISC DATA REGISTER ................................................................................................................................................. 52
7
SERIAL EEPROM SPECIFICATION..........................................................................................................................53
EEPROM DATA ORGANISATION ..................................................................................................................................... 53
ZONE 0: HEADER ............................................................................................................................................................... 53
ZONE 1: CARD INFORMATION STRUCTURE ................................................................................................................. 54
ZONE 2: LOCAL REGISTER CONFIGURATION .............................................................................................................. 54
ZONE 3: FUNCTION ACCESS (UART) ............................................................................................................................. 55
7.1
7.2
7.3
7.4
7.5
8
OPERATINGCONDITIONS...........................................................................................................................................56
9
9.1
DC ELECTRICAL CHARACTERISTICS...................................................................................................................57
3.0V TO 3.6V OPERATI ON................................................................................................................................................. 57
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