Datasheet > OR3C80-5BC600I

OR3C80-5BC600I

更新时间： 2024-02-27 10:08:10

品牌	Logo	应用领域
其他 - ETC		现场可编程门阵列可编程逻辑栅时钟
页数	文件大小	规格书
210页	4390K
描述
Field Programmable Gate Array (FPGA)

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

OR3C80-5BC600I 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA, BGA600,35X35,50
针数：	600	Reach Compliance Code：	unknown
风险等级：	5.92	Is Samacsys：	N
最大时钟频率：	80 MHz	JESD-30 代码：	S-PBGA-B600
JESD-609代码：	e0	输入次数：	444
逻辑单元数量：	3872	输出次数：	444
端子数量：	600	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA600,35X35,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	5 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	子类别：	Field Programmable Gate Arrays
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
Base Number Matches：	1

OR3C80-5BC600I 数据手册

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

PLC Logic

Description

Each PFU within a PLC contains eight 4-input (16-bit)

look-up tables (LUTs), eight latches/flip-flops (FFs),

and one additional flip-flop that may be used indepen-

dently or with arithmetic functions.

FPGA Overview

The ORCA Series 3 FPGAs are a new generation of

SRAM-based FPGAs built on the successful OR2C/

TxxA FPGA Series from Lucent Technologies Micro-

electronics Group, with enhancements and innovations

geared toward today’s high-speed designs and tomor-

row’s systems on a single chip. Designed from the start

to be synthesis friendly and to reduce place and route

times while maintaining the complete routability of the

ORCA 2C/2T devices, Series 3 more than doubles the

logic available in each logic block and incorporates sys-

tem-level features that can further reduce logic require-

ments and increase system speed. ORCA Series 3

devices contain many new patented enhancements

and are offered in a variety of packages, speed grades,

and temperature ranges.

The PFU is organized in a twin-quad fashion: two sets

of four LUTs and FFs that can be controlled indepen-

dently. LUTs may also be combined for use in arith-

metic functions using fast-carry chain logic in either

4-bit or 8-bit modes. The carry-out of either mode may

be registered in the ninth FF for pipelining. Each PFU

may also be configured as a synchronous 32 x 4 sin-

gle- or dual-port RAM or ROM. The FFs (or latches)

may obtain input from LUT outputs or directly from

invertible PFU inputs, or they can be tied high or tied

low. The FFs also have programmable clock polarity,

clock enables, and local set/reset.

The SLIC is connected to PLC routing resources and to

the outputs of the PFU. It contains 3-state, bidirectional

buffers and logic to perform up to a 10-bit AND function

for decoding, or an AND-OR with optional INVERT

(AOI) to perform PAL-like functions. The 3-state drivers

in the SLIC and their direct connections to the PFU out-

puts make fast, true 3-state buses possible within the

FPGA, reducing required routing and allowing for real-

world system performance.

The ORCA Series 3 FPGAs consist of three basic ele-

ments: programmable logic cells (PLCs), programma-

ble input/output cells (PICs), and system-level features.

An array of PLCs is surrounded by PICs. Each PLC

contains a programmable function unit (PFU), a sup-

plemental logic and interconnect cell (SLIC), local rout-

ing resources, and configuration RAM. Most of the

FPGA logic is performed in the PFU, but decoders,

PAL-like functions, and 3-state buffering can be per-

formed in the SLIC. The PICs provide device inputs

and outputs and can be used to register signals and to

perform input demultiplexing, output multiplexing, and

other functions on two output signals. Some of the sys-

tem-level functions include the new microprocessor

interface (MPI) and the programmable clock manager

(PCM).

Lucent Technologies Inc.

1...4 5 678 9 10...210

下载PDF

与OR3C80-5BC600I相关器件

型号	品牌	描述	获取价格	数据表
OR3C80-5PS208	AGERE	3C and 3T Field-Programmable Gate Arrays	获取价格
OR3C80-5PS208	LATTICE	Field Programmable Gate Array, 3872-Cell, CMOS, PQFP208	获取价格
OR3C80-5PS208-DB	LATTICE	Field Programmable Gate Array, 484 CLBs, 116000 Gates, 80MHz, 3872-Cell, CMOS, PQFP208, PL	获取价格
OR3C805PS208-DB	LATTICE	FPGA, 484 CLBS, 116000 GATES, PQFP208, PLASTIC, SQFP2-208	获取价格
OR3C80-5PS208I	AGERE	3C and 3T Field-Programmable Gate Arrays	获取价格
OR3C80-5PS208I	LATTICE	Field Programmable Gate Array, 3872-Cell, CMOS, PQFP208	获取价格

与OR3C80-5BC600I相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

17
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

16
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

14
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

11

产品中心

服务支持

精选活动

关于我们

帮助中心

OR3C80-5BC600I

OR3C80-5BC600I 技术参数

OR3C80-5BC600I 数据手册

与OR3C80-5BC600I相关器件

与OR3C80-5BC600I相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

OR3C80-5BC600I

OR3C80-5BC600I 技术参数

OR3C80-5BC600I 数据手册

与OR3C80-5BC600I相关器件

与OR3C80-5BC600I相关文章

您还可以找

您在本页遇到什么问题？