Datasheet > OR3L165B-7BC432

OR3L165B-7BC432

更新时间： 2024-02-23 23:37:29

品牌	Logo	应用领域
莱迪思 - LATTICE		栅可编程逻辑
页数	文件大小	规格书
88页	1435K
描述
Field Programmable Gate Array, 8192-Cell, CMOS, PBGA432

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

OR3L165B-7BC432 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	BGA, BGA432,31X31,50	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	S-PBGA-B432
JESD-609代码：	e0	输入次数：	326
逻辑单元数量：	8192	输出次数：	326
端子数量：	432	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA432,31X31,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	2.5,3.3 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	子类别：	Field Programmable Gate Arrays
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM

OR3L165B-7BC432 数据手册

Data Addendum

January 2002

ORCA^®OR3LxxxB Series

Field-Programmable Gate Arrays

shared inputs and the logic ﬂexibility of LUTs with

independent inputs.

Introduction

■ Fast-carry logic and routing to adjacent PFUs for

nibble-wide, byte-wide, or longer arithmetic func-

tions, with the option to register the PFU carry-out.

■ Softwired LUTs (SWL) allow fast cascading of up

to three levels of LUT logic in a single PFU.

■ Supplemental logic and interconnect cell (SLIC)

provides 3-statable buffers, up to 10-bit decoder,

and PAL*-like AND-OR-INVERT (AOI) in each pro-

grammable logic cell (PLC).

■ Abundant hierarchical routing resources based on

routing two data nibbles and two control lines per

set provide for faster place and route implementa-

tions and less routing delay.

■ Individually programmable drive capability: 12 mA

sink/6 mA source or 6 mA sink/3 mA source.

■ Built-in boundary scan (IEEE ^†1149.1 JTAG) and

testability function to 3-state all I/O pins.

■ Enhanced system clock routing for low-skew, high-

speed clocks originating on-chip or at any I/O.

■ Up to four ExpressCLK inputs allow extremely fast

clocking of signals on- and off-chip plus access to

internal general clock routing.

This data addendum refers to the information found

in the ORCA Series 3C and 3T Field-Programmable

Gate Arrays Data Sheet.

Features

■ High-performance, cost-effective, 0.25 µm 5-level

metal technology.

■ 2.5 V internal supply voltage and 3.3 V I/O supply

voltage for speed and compatibility.

■ Up to 340,000 usable gates^‡in 0.25 µm.

■ Up to 612 user I/Os in 0.25 µm. (OR3LxxxB I/Os

are 5 V tolerant to allow interconnection to both

3.3 V and 5 V devices, selectable on a per-pin

basis, when using 3.3 V I/O supply.)

■ Twin-quad programmable function unit (PFU)

architecture with eight 16-bit look-up tables (LUTs)

per PFU, organized in two nibbles for use in nibble-

or byte-wide functions. Allows for mixed arithmetic

and logic functions in a single PFU.

■ Nine user registers per PFU, one following each

LUT, plus one extra. All have programmable clock

enable and local set/reset, plus a global set/reset

that can be disabled per PFU.

■ StopCLK feature to glitchlessly stop/start the

ExpressCLKs independently by user command.

* PAL is a trademark of Lattice Semiconductor

†IEEE is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

■ Flexible input structure (FINS) of the PFUs pro-

vides a routability enhancement for LUTs with

Table 1. ORCA OR3LxxxB Series FPGAs

System

Max User

RAM

Process

Technology

Device

LUTs

Registers

User I/Os Array Size

Gates^‡

OR3L165B 120K—244K

8192

10752

14820

131K

185K

516

612

32 × 32

38 × 38

0.25 µm/5 LM

OR3L225B 166K—340K 11552

‡The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.

The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and

12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (three FFs, fast-capture latch, output

logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 × 4 RAM

(or 512 gates) per PFU.

12 3 4 5 6 7...88

下载PDF

与OR3L165B-7BC432相关器件

型号	品牌	描述	获取价格	数据表
OR3L165B7BC432-DB	LATTICE	Field Programmable Gate Array, 1024 CLBs, 120000 Gates, 266.4MHz, 8192-Cell, CMOS, PBGA432	获取价格
OR3L165B7BC432-DB	ROCHESTER	FPGA, 1024 CLBS, 120000 GATES, 266.4 MHz, PBGA432, EBGA-432	获取价格
OR3L165B7BC432I-DB	LATTICE	Field Programmable Gate Array, 1024 CLBs, 120000 Gates, 266.4MHz, 8192-Cell, CMOS, PBGA432	获取价格
OR3L165B7BC432I-DB	ROCHESTER	FPGA, 1024 CLBS, 120000 GATES, 266.4 MHz, PBGA432, EBGA-432	获取价格
OR3L165B-7BM680	LATTICE	Field Programmable Gate Array, 8192-Cell, CMOS, PBGA680	获取价格
OR3L165B-7BM680I	LATTICE	Field Programmable Gate Array, 8192-Cell, CMOS, PBGA680	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

OR3L165B-7BC432

OR3L165B-7BC432 技术参数

OR3L165B-7BC432 数据手册

与OR3L165B-7BC432相关器件

与OR3L165B-7BC432相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

OR3L165B-7BC432

OR3L165B-7BC432 技术参数

OR3L165B-7BC432 数据手册

与OR3L165B-7BC432相关器件

与OR3L165B-7BC432相关文章

您还可以找

您在本页遇到什么问题？