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NLVHC125ADTR2G PDF预览

NLVHC125ADTR2G

更新时间： 2024-11-25 11:01:43
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
7页 113K
描述
Quad Non-inverting Buffer, 3-State

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NLVHC125ADTR2G 数据手册

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MC74HC125A,  
MC74HC126A  
Quad 3-State Noninverting  
Buffers  
High−Performance Silicon−Gate CMOS  
http://onsemi.com  
The MC74HC125A and MC74HC126A are identical in pinout to  
the LS125 and LS126. The device inputs are compatible with standard  
CMOS outputs; with pullup resistors, they are compatible with  
LSTTL outputs.  
The HC125A and HC126A noninverting buffers are designed to be  
used with 3−state memory address drivers, clock drivers, and other  
bus−oriented systems. The devices have four separate output enables  
that are active−low (HC125A) or active−high (HC126A).  
SOIC−14 NB  
D SUFFIX  
CASE 751A  
TSSOP−14  
DT SUFFIX  
CASE 948G  
PIN ASSIGNMENT  
Features  
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
• Output Drive Capability: 15 LSTTL Loads  
• Outputs Directly Interface to CMOS, NMOS, and TTL  
• Operating Voltage Range: 2.0 to 6.0 V  
Y1  
3
4
A4  
OE2  
11 Y4  
• Low Input Current: 1.0 mA  
A2  
Y2  
5
6
10 OE3  
• High Noise Immunity Characteristic of CMOS Devices  
• In Compliance with the JEDEC Standard No. 7 A Requirements  
• Chip Complexity: 72 FETs or 18 Equivalent Gates  
9
8
A3  
Y3  
GND  
7
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
MARKING DIAGRAMS  
14  
14  
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
HC  
12xA  
ALYWG  
G
HC12xAG  
AWLYWW  
Compliant  
LOGIC DIAGRAM  
1
1
HC125A  
HC126A  
SOIC−14 NB  
TSSOP−14  
Active−Low Output Enables  
Active−High Output Enables  
x
= 5, 6  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
2
3
2
3
A1  
A1  
Y1  
Y2  
Y3  
Y1  
Y2  
Y3  
1
5
1
5
W, WW = Work Week  
OE1  
A2  
OE1  
A2  
G or G  
= Pb−Free Package  
6
6
(Note: Microdot may be in either location)  
4
9
4
9
OE2  
A3  
OE2  
A3  
FUNCTION TABLE  
HC125A  
HC126A  
8
8
Inputs Output  
Inputs Output  
A
OE  
Y
A
OE  
Y
10  
12  
10  
12  
OE3  
A4  
OE3  
A4  
H
L
X
L
L
H
H
L
Z
H
L
X
H
H
L
H
L
Z
11  
11  
Y4  
Y4  
13  
13  
OE4  
OE4  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
PIN 14 = V  
CC  
PIN 7 = GND  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
August, 2014 − Rev. 15  
MC74HC125A/D  
1234567

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