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NLU2G14CMUTCG PDF预览

NLU2G14CMUTCG

更新时间: 2024-10-01 21:16:15
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
10页 132K
描述
IC INVERT GATE, Gate

NLU2G14CMUTCG 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DFN包装说明:VSON, SOLCC6,.04,14
针数:6Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.7
系列:2GJESD-30 代码:S-PDSO-N6
长度:1 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.004 A
湿度敏感等级:1功能数量:2
输入次数:1端子数量:6
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装等效代码:SOLCC6,.04,14封装形状:SQUARE
封装形式:SMALL OUTLINE, VERY THIN PROFILE包装方法:TAPE AND REEL
电源:1.8/5 VProp。Delay @ Nom-Sup:20.5 ns
传播延迟(tpd):20.5 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:0.55 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Gold/Palladium (Ni/Au/Pd)
端子形式:NO LEAD端子节距:0.35 mm
端子位置:DUAL宽度:1 mm
Base Number Matches:1

NLU2G14CMUTCG 数据手册

 浏览型号NLU2G14CMUTCG的Datasheet PDF文件第2页浏览型号NLU2G14CMUTCG的Datasheet PDF文件第3页浏览型号NLU2G14CMUTCG的Datasheet PDF文件第4页浏览型号NLU2G14CMUTCG的Datasheet PDF文件第5页浏览型号NLU2G14CMUTCG的Datasheet PDF文件第6页浏览型号NLU2G14CMUTCG的Datasheet PDF文件第7页 
NLU2G14  
Dual Schmitt-Trigger  
Inverter  
The NLU2G14 MiniGatet is an advanced highspeed CMOS dual  
Schmitttrigger inverter in ultrasmall footprint.  
The NLU2G14 input and output structures provide protection when  
voltages up to 7.0 V are applied, regardless of the supply voltage.  
The NLU2G14 can be used to enhance noise immunity or to square  
up slowly changing waveforms.  
http://onsemi.com  
MARKING  
DIAGRAMS  
Features  
UDFN6  
1.2 x 1.0  
CASE 517AA  
High Speed: t = 4.0 ns (Typ) @ V = 5.0 V  
PD  
CC  
DM  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
1
1
Power Down Protection Provided on inputs  
Balanced Propagation Delays  
ULLGA6  
1.0 x 1.0  
CASE 613AD  
DM  
DM  
DM  
Overvoltage Tolerant (OVT) Input and Output Pins  
UltraSmall Packages  
These are PbFree Devices  
ULLGA6  
1.2 x 1.0  
CASE 613AE  
1
IN A1  
GND  
IN A2  
1
2
3
6
5
OUT Y1  
ULLGA6  
1.45 x 1.0  
CASE 613AF  
V
CC  
1
UDFN6  
1.0 x 1.0  
CASE 517BX  
4
OUT Y2  
X M  
X M  
1
Figure 1. Pinout (Top View)  
UDFN6  
1.45 x 1.0  
CASE 517AQ  
1
IN A1  
IN A2  
OUT Y1  
OUT Y2  
1
1
D
M
= Device Marking  
= Date Code  
Figure 2. Logic Symbol  
PIN ASSIGNMENT  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
1
2
3
4
5
6
IN A1  
GND  
FUNCTION TABLE  
IN A2  
A
Y
OUT Y2  
V
CC  
L
H
H
L
OUT Y1  
© Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
July, 2012 Rev. 4  
NLU2G14/D  

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