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NLAS4052DR2 PDF预览

NLAS4052DR2

更新时间: 2024-02-07 10:38:37
品牌 Logo 应用领域
安森美 - ONSEMI 解复用器
页数 文件大小 规格书
16页 130K
描述
Analog Multiplexer/ Demultiplexer

NLAS4052DR2 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:7.57模拟集成电路 - 其他类型:DIFFERENTIAL MULTIPLEXER
JESD-30 代码:R-PDSO-G16长度:9.9 mm
负电源电压最大值(Vsup):-5.5 V负电源电压最小值(Vsup):
标称负供电电压 (Vsup):-3 V信道数量:4
功能数量:1端子数量:16
标称断态隔离度:93 dB通态电阻匹配规范:15 Ω
最大通态电阻 (Ron):37 Ω最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:-3.3/GND,3.3/5 V认证状态:Not Qualified
座面最大高度:1.75 mm最大信号电流:0.05 A
子类别:Multiplexer or Switches最大供电电流 (Isup):0.08 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):3 V表面贴装:YES
最长断开时间:28 ns最长接通时间:28 ns
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

NLAS4052DR2 数据手册

 浏览型号NLAS4052DR2的Datasheet PDF文件第2页浏览型号NLAS4052DR2的Datasheet PDF文件第3页浏览型号NLAS4052DR2的Datasheet PDF文件第4页浏览型号NLAS4052DR2的Datasheet PDF文件第5页浏览型号NLAS4052DR2的Datasheet PDF文件第6页浏览型号NLAS4052DR2的Datasheet PDF文件第7页 
NLAS4052  
Analog Multiplexer/  
Demultiplexer  
Double–Pole, 4–Position  
Plus Common Off  
http://onsemi.com  
MARKING DIAGRAMS  
The NLAS4052 is an improved version of the MC14052 and  
MC74HC4052 fabricated in sub–micron Silicon Gate CMOS  
technology for lower R  
resistance and improved linearity with  
DS(on)  
low current. This device may be operated either with a single supply or  
16  
dual supply up to ±3 V to pass a 6 V signal without coupling  
9
PP  
capacitors.  
NLAS4052  
AWLYWW  
When operating in single supply mode, it is only necessary to tie  
SO–16  
D SUFFIX  
CASE 751B  
1
8
V , pin 7 to ground. For dual supply operation, V is tied to a  
EE  
EE  
negative voltage, not to exceed maximum ratings.  
16  
9
Improved R Specifications  
DS(on)  
Pin for Pin Replacement for MAX4052 and MAX4052A  
NLAS  
4052  
ALYW  
– One Half the Resistance Operating at 5.0 Volts  
TSSOP–16  
DT SUFFIX  
CASE 948F  
Single or Dual Supply Operation  
– Single 2.5–5 Volt Operation, or Dual ±3 Volt Operation  
1
8
9
– With V of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,  
No Translators Needed  
– Address and Inhibit pins are Logic is Over–Voltage Tolerant and –  
CC  
16  
May Be Driven Up +6 V Regardless of V  
NLAS  
4052  
ALYW  
CC  
Address and Inhibit pins are Standard TTL Compatible  
QSOP–16  
QS SUFFIX  
CASE 492  
– Greatly Improved Noise Margin Over MAX4052 and MAX4052A  
Improved Linearity Over Standard HC4052 Devices  
1
8
Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin  
A
WL, L  
Y
= Assembly Location  
= Wafer Lot  
= Year  
Packages  
WW, W = Work Week  
ORDERING INFORMATION  
Device  
NLAS4052DR2  
NLAS4052DTR2  
NLAS4052QSR  
Package  
Shipping  
2500 Units/Reel  
SO–16  
TSSOP–16 2500 Units/Reel  
QSOP–16 2500 Units/Reel  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
June, 2002 – Rev. 1  
NLAS4052/D  

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