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NLAS4053DTG PDF预览

NLAS4053DTG

更新时间: 2024-11-19 03:46:23
品牌 Logo 应用领域
安森美 - ONSEMI 解复用器
页数 文件大小 规格书
14页 137K
描述
Analog Multiplexer/Demultiplexer

NLAS4053DTG 技术参数

是否无铅: 不含铅生命周期:End Of Life
零件包装代码:TSSOP包装说明:TSSOP, TSSOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.69模拟集成电路 - 其他类型:SINGLE-ENDED MULTIPLEXER
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm湿度敏感等级:1
负电源电压最大值(Vsup):-5.5 V负电源电压最小值(Vsup):
标称负供电电压 (Vsup):-3 V信道数量:2
功能数量:3端子数量:16
标称断态隔离度:93 dB通态电阻匹配规范:15 Ω
最大通态电阻 (Ron):37 Ω最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:-3,3/5 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大信号电流:0.05 A子类别:Multiplexer or Switches
最大供电电流 (Isup):0.08 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):3 V
表面贴装:YES最长断开时间:28 ns
最长接通时间:28 ns切换:BREAK-BEFORE-MAKE
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
Base Number Matches:1

NLAS4053DTG 数据手册

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NLAS4053  
Analog Multiplexer/  
Demultiplexer  
Triple 2:1 Analog Switch−Multiplexer  
Improved Process, Sub−Micron Silicon  
Gate CMOS  
http://onsemi.com  
MARKING  
DIAGRAMS  
The NLAS4053 is an improved version of the MC14053 and  
MC74HC4053 fabricated in sub−micron Silicon Gate CMOS  
technology for lower R  
low current. This device may be operated either with a single supply or  
dual supply up to 3.0 V to pass a 6 V signal without coupling  
capacitors.  
resistance and improved linearity with  
DS(on)  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
NLAS4053G  
AWLYWW  
PP  
When operating in single supply mode, it is only necessary to tie  
1
V
EE  
, pin 7 to ground. For dual supply operation, V is tied to a  
EE  
negative voltage, not to exceed maximum ratings. Pin for pin  
compatible with all industry standard versions of ‘4053.’  
16  
NLAS  
4053  
ALYWG  
G
TSSOP−16  
DT SUFFIX  
CASE 948F  
Features  
Improved R  
Specifications  
DS(on)  
1
Pin for Pin Replacement for MAX4053 and MAX4053A  
− One Half the Resistance Operating at 5.0 Volts  
A
L, WL  
Y
= Assembly Location  
= Wafer Lot  
Single or Dual Supply Operation  
= Year  
W, WW = Work Week  
− Single 3−5 Volt Operation, or Dual 3.0 Volt Operation  
− With V of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,  
CC  
G
G
= Pb−Free Package  
= Pb−Free Package  
(Note: Microdot may be in either location)  
No Translators Needed  
− Address and Inhibit Pins are Over−Voltage Tolerant and May Be  
Driven Up +6.0 V Regardless of V  
CC  
− Greatly Improved Noise Margin Over MAX4053 and MAX4053A  
Improved Linearity Over Standard HC4053 Devices  
Popular SOIC and the Space Saving TSSOP Packages  
Pb−Free Packages are Available*  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
November, 2005 − Rev. 2  
NLAS4053/D  

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