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NL27WZ07DTT3 PDF预览

NL27WZ07DTT3

更新时间: 2023-07-15 00:00:00
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
12页 126K
描述
IC,LOGIC GATE,DUAL BUFFER,LCX/LVC-CMOS,TSOP,6PIN,PLASTIC

NL27WZ07DTT3 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:TSOP, TSOP6,.11,37Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-PDSO-G6
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:BUFFER最大I(ol):0.024 A
端子数量:6最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY封装代码:TSOP
封装等效代码:TSOP6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE包装方法:TAPE AND REEL
电源:3.3 VProp。Delay @ Nom-Sup:4.8 ns
认证状态:Not Qualified施密特触发器:NO
子类别:Gates标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL

NL27WZ07DTT3 数据手册

 浏览型号NL27WZ07DTT3的Datasheet PDF文件第2页浏览型号NL27WZ07DTT3的Datasheet PDF文件第3页浏览型号NL27WZ07DTT3的Datasheet PDF文件第4页浏览型号NL27WZ07DTT3的Datasheet PDF文件第5页浏览型号NL27WZ07DTT3的Datasheet PDF文件第6页浏览型号NL27WZ07DTT3的Datasheet PDF文件第7页 
NL27WZ07  
Product Preview  
Dual Buffer with Open Drain  
Outputs  
The NL27WZ07 is a high performance dual buffer with open drain  
outputs operating from a 2.3 to 5.5 V supply.  
http://onsemi.com  
The internal circuit is composed of multiple stages, including an open  
drain output which provides the capability to set output switching level.  
This allows the NL27WZ07 to be used to interface 5 V circuits to circuits  
MARKING  
DIAGRAMS  
of any voltage between V and 7 V using an external resistor and power  
CC  
supply.  
Current drive capability is 24 mA at the outputs.  
SC–88 / SOT–363/SC–70  
DF SUFFIX  
M7d  
Extremely High Speed: t 2.5 ns (typical) at V = 5 V  
PD  
CC  
CASE 419B  
Designed for 2.3 V to 5.5 V V Operation  
CC  
Over Voltage Tolerant Inputs  
Pin 1  
LVTTL Compatible – Interface Capability With 5 V TTL Logic with  
d = Date Code  
V
CC  
= 3 V  
LVCMOS Compatible  
24 mA Balanced Output Sink and Source Capability  
TSOP–6/SOT–23/SC–59  
DT SUFFIX  
M7d  
Near Zero Static Supply Current Substantially Reduces System  
Power Requirements  
CASE 318G  
Pin 1  
d = Date Code  
IN A1  
GND  
IN A2  
1
2
3
6
5
4
OUT Y1  
PIN ASSIGNMENT  
1
2
3
4
IN A1  
GND  
V
CC  
IN A2  
OUT Y2  
5
6
V
CC  
OUT Y2  
OUT Y1  
FUNCTION TABLE  
Figure 1. 6–Lead SOT–363 Pinout (Top View)  
A Input  
Y Output  
L
L
Z
1
1
IN A1  
IN A2  
OUT Y1  
OUT Y2  
H
Figure 2. Logic Symbol  
ORDERING INFORMATION  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
December, 2000 – Rev. 0  
NL27WZ07/D  

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