Datasheet > NL27WZ125_06

NL27WZ125_06

更新时间： 2024-01-20 20:14:23

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
5页	72K
描述
Dual Buffer with 3−State Outputs

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NL27WZ125_06 数据手册

NL27WZ125

Dual Buffer with 3−State

Outputs

The NL27WZ125 is a high performance dual noninverting buffer

operating from a 1.65 V to 5.5 V supply.

Features

http://onsemi.com

MARKING

• Extremely High Speed: t 2.6 ns (typical) at V = 5 V

• Designed for 1.65 V to 5.5 V V Operation

DIAGRAM

• Over Voltage Tolerant Inputs and Outputs

• LVTTL Compatible − Interface Capability With 5 V TTL Logic with

= 3 V

M0 M G

US8

• LVCMOS Compatible

US SUFFIX

CASE 493

• 24 mA Balanced Output Sink and Source Capability

• Near Zero Static Supply Current Substantially Reduces System

Power Requirements

= Device Code

= Date Code*

= Pb−Free Package

• 3−State OE Input is Active−Low

• Replacement for NC7WZ125

• Chip Complexity = 72 FETs

• Pb−Free Package is Available

(Note: Microdot may be in either location)

*Date Code orientation may vary depending upon

manufacturing location.

PIN ASSIGNMENT

Function

GND

FUNCTION TABLE

Input

Figure 1. Pinout (Top View)

Output

X = Don’t Care

n = 1, 2

Figure 2. Logic Symbol

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Publication Order Number:

April, 2006 − Rev. 5

NL27WZ125/D

12 3 4 5

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