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NL27WZ126 PDF预览

NL27WZ126

更新时间: 2024-11-25 03:46:23
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
6页 73K
描述
Dual Buffer with 3−State Outputs

NL27WZ126 数据手册

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NL27WZ126  
Dual Buffer with 3−State  
Outputs  
The NL27WZ126 is a high performance dual noninverting buffer  
operating from a 1.65 V to 5.5 V supply.  
Features  
http://onsemi.com  
Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V  
PD  
CC  
MARKING  
DIAGRAM  
Designed for 1.65 V to 5.5 V V Operation  
CC  
Over Voltage Tolerant Inputs and Outputs  
8
LVTTL Compatible − Interface Capability With 5.0 V TTL Logic  
with V = 3.0 V  
CC  
US8  
US SUFFIX  
CASE 493  
M2 M G  
LVCMOS Compatible  
8
G
24 mA Balanced Output Sink and Source Capability  
1
Near Zero Static Supply Current Substantially Reduces System  
Power Requirements  
1
3−State OE Input is Active−High  
M2  
M
G
= Device Code  
= Date Code*  
= Pb−Free Package  
Replacement for NC7WZ126  
Chip Complexity = 72 FETs  
Pb−Free Package is Available  
(Note: Microdot may be in either location)  
*Date Code orientation may vary depending upon  
manufacturing location.  
PIN ASSIGNMENT  
8
7
6
OE  
A
V
CC  
1
2
1
Pin  
Function  
1
OE  
OE  
1
2
2
3
4
5
6
7
8
A
Y
1
2
Y
1
Y
2
3
4
GND  
A
2
Y
1
5
A
2
GND  
OE  
2
V
CC  
Figure 1. Pinout (Top View)  
FUNCTION TABLE  
Input  
Output  
A
1
OE  
H
A
Y
n
n
n
1
Y
Y
1
OE  
EN  
1
H
H
A
2
H
L
L
Z
2
OE  
2
L
X
Figure 2. Logic Symbol  
X = Don’t Care  
n = 1, 2  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
April, 2006 − Rev. 6  
NL27WZ126/D  

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