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NL17SG373DFT2G PDF预览

NL17SG373DFT2G

更新时间: 2024-09-29 01:15:19
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
10页 119K
描述
Low-Power D-Type Low-Power D-Type

NL17SG373DFT2G 数据手册

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NL17SG373  
Low-Power D-Type  
Transparent Latch with  
3-State Output  
The NL17SG373 MiniGateis an advanced high−speed CMOS  
D−Type Transparent Latch with 3−State Output in ultra−small  
footprint.  
www.onsemi.com  
The NL17SG373 input structures provide protection when voltages  
up to 5.5 V are applied, regardless of the supply voltage.  
This device is fully specified for partial power−down applications  
MARKING  
DIAGRAMS  
6
using I . The I  
circuitry disables the output, preventing the  
OFF  
OFF  
SC−88  
DF SUFFIX  
CASE 419B  
damaging backflow current through the device when it is powered  
down.  
1
AG M G  
G
Features  
1
Wide Operating V Range: 0.9 V to 3.6 V  
CC  
AG = Device Code  
High Speed: t = 2.4 ns (Typ) @ V = 3.0 V, C = 15 pF  
PD  
CC  
L
M
G
= Date Code*  
= Pb−Free Package  
Low Power Dissipation: I = 0.5 mA (Max) at T = 25°C  
CC  
A
5.5 V Overvoltage Tolerant (OVT) Input Pins  
(Note: Microdot may be in either location)  
Ultra−Small Packages  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
These Devices are Pb−Free and are RoHS Compliant  
PIN ASSIGNMENT  
Pin  
1
Function  
LE  
GND  
D
2
3
Figure 1. SC88 (Top View)  
4
Q
5
V
CC  
6
OE  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
May, 2018 − Rev. 2  
NL17SG373/D  

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