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NE564N PDF预览

NE564N

更新时间: 2024-11-27 20:14:35
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管
页数 文件大小 规格书
9页 109K
描述
IC PHASE LOCKED LOOP, 50 MHz, PDIP16, PLASTIC, DIP-16, PLL or Frequency Synthesis Circuit

NE564N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-16
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.87
Is Samacsys:N模拟集成电路 - 其他类型:PHASE LOCKED LOOP
JESD-30 代码:R-PDIP-T16长度:19.025 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:4.2 mm
子类别:PLL or Frequency Synthesis Circuits最大供电电流 (Isup):60 mA
标称供电电压 (Vsup):5 V表面贴装:NO
技术:BIPOLAR温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

NE564N 数据手册

 浏览型号NE564N的Datasheet PDF文件第2页浏览型号NE564N的Datasheet PDF文件第3页浏览型号NE564N的Datasheet PDF文件第4页浏览型号NE564N的Datasheet PDF文件第5页浏览型号NE564N的Datasheet PDF文件第6页浏览型号NE564N的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
Phase-locked loop  
NE/SE564  
DESCRIPTION  
PIN CONFIGURATIONS  
The NE/SE564 is a versatile, high guaranteed frequency  
phase-locked loop designed for operation up to 50MHz. As shown  
in the Block Diagram, the NE/SE564 consists of a VCO, limiter,  
phase comparator, and post detection processor.  
D, N Packages  
1
2
3
4
5
6
7
8
16  
V+  
TTL OUTPUT  
LOOP GAIN CONTROL  
15  
14  
HYSTERESIS SET  
FEATURES  
Operation with single 5V supply  
INPUT TO PHASE COMP  
FROM VCO  
ANALOG OUT  
13 FREQ. SET CAP  
LOOP FILTER  
LOOP FILTER  
TTL-compatible inputs and outputs  
Guaranteed operation to 50MHz  
External loop gain control  
12  
11  
10  
9
FREQ. SET CAP  
VCO OUT 2  
FM/RF INPUT  
Reduced carrier feedthrough  
BIAS FILTER  
GND  
V+  
VCO OUT TTL  
No elaborate filtering needed in FSK applications  
Can be used as a modulator  
TOP VIEW  
Variable loop gain (externally controlled)  
SR01025  
Figure 1. Pin Configuration  
Signal generators  
APPLICATIONS  
High speed modems  
FSK receivers and transmitters  
Frequency Synthesizers  
Various satcom/TV systems  
pin configuration  
ORDERING INFORMATION  
DESCRIPTION  
TEMPERATURE RANGE  
0 to +70°C  
ORDER CODE  
NE564D  
DWG #  
SOT109-1  
SOT38-4  
SOT38-4  
16-Pin Plastic Small Outline (SO) Package  
16-Pin Plastic Dual In-Line Package (DIP)  
16-Pin Plastic Dual In-Line Package (DIP)  
0 to +70°C  
NE564N  
-55 to +125°C  
SE564N  
BLOCK DIAGRAM  
V
+
14  
4
5
1
PHASE  
COMPARATOR  
2
LIMITER  
7
6
DC  
RETRIEVER  
3
AMPLIFIER  
SCHMITT  
TRIGGER  
11  
16  
9
POST DETECTION  
PROCESSOR  
VCO  
15  
10  
8
12  
13  
SR01026  
Figure 2. Block Diagram  
1
1994 Aug 31  
853-0908 13720  

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