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NE5565N PDF预览

NE5565N

更新时间: 2024-02-21 17:58:14
品牌 Logo 应用领域
恩智浦 - NXP 电子控制器
页数 文件大小 规格书
6页 75K
描述
Electronic ballast controller circuit

NE5565N 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:20
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
模拟集成电路 - 其他类型:FLUORESCENT LIGHT CONTROLLER控制模式:VOLTAGE-MODE
控制技术:PULSE WIDTH MODULATION最大输入电压:14 V
最小输入电压:9.3 V标称输入电压:12.7 V
JESD-30 代码:R-PDIP-T20长度:26.73 mm
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:
最大输出电流:0.25 A标称输出电压:7.42 V
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified座面最大高度:4.2 mm
最大供电电流 (Isup):18 mA表面贴装:NO
切换器配置:SINGLE技术:BIPOLAR
温度等级:OTHER端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

NE5565N 数据手册

 浏览型号NE5565N的Datasheet PDF文件第1页浏览型号NE5565N的Datasheet PDF文件第2页浏览型号NE5565N的Datasheet PDF文件第4页浏览型号NE5565N的Datasheet PDF文件第5页浏览型号NE5565N的Datasheet PDF文件第6页 
Philips Semiconductors  
Product specification  
Electronic ballast controller circuit  
NE5565  
external LC network driven by the bridge. At frequencies above  
resonance the primary voltage of the half-bridge LC load network  
leads the primary current in phase. The protection logic senses the  
LC network current phase relative to the half-bridge gate drive  
voltage to determine if a resonant condition exists. The Iprim input  
voltage represents the primary current signal from the external LC  
network. If the voltage at Iprim is more positive than -100mV when  
the gate drive signal is high, then a fault condition exists and the  
half-bridge oscillator frequency is swept high.  
triggers the over current protection circuit this turns off the OUT  
P
output and forces the external capacitor connected to D  
to  
MAX  
discharge when an over current condition occurs in the PFC input  
circuit. An over current condition is usually produced during the turn  
on transient of the SMPS or when the AC line voltage has a power  
interruption.  
Power Factor Amplifier  
Senses the phase and amplitude of a peak rectified AC line voltage  
in order to modulate the duty cycle of the PFC power switch. This is  
done to improve the sinusoidal wave shape of the AC line current.  
The power factor input is provided by the PF input pin. The voltage  
at this pin is 1V when the AC line voltage reaches its peak and 0V  
when the AC voltage is at its 0V crossing.  
Half-Bridge Oscillator  
Is a triangle wave generator used to produce a square wave signal  
for driving the half-bridge buffer circuit. The triangle wave appears  
on the C capacitor output pin. The oscillator frequency is governed  
t
by the value of the resistor connected to the R input and the value  
t
DC Error Amplifier  
of the C capacitor.  
t
Provides negative feedback control of the PFC DC output voltage.  
The DC pin senses the DC output voltage of the PFC through an  
external resistor voltage divider and filter network. The reference  
Output Buffer Drive  
Convert the low level logic signals from the half-bridge oscillator and  
pulse width modulator into a 10V drive signal for the power switches.  
voltage for the DC error amplifier is V . The output of the  
REF  
The OUT half-bridge buffer/drive circuit will drive an external level  
shift scheme which will then be used to operate the half-bridge  
amplifier is available at the DC out pin and an external capacitor is  
connected to this pin in order to remove switching frequency noise  
before its signal is applied to the pulse width modulator in the PWM  
oscillator circuit.  
H
power switches. The OUT output may directly drive a power  
P
MOSFET switch or an external level shift/power MOSFET  
combination.  
Lamp Current Rectifier  
Pulse Width Modulator  
Generates a ramp voltage used to control the duty cycle of the PFC  
SMPS. The frequency of the pulse width modulator is set by the  
Is used to provide negative feedback control of the average lamp  
current. An external lamp current transformer and load resistor are  
used to convert the lamp current signal into a voltage. This voltage  
is applied to the lamp current input pins, Li1 and Li2. The full wave  
half-bridge oscillator. The ramp voltage appears at the C output. It  
P
is synchronized to the half-bridge oscillator so that the beginning of  
rectified output is provided at C  
pin. External resistors and a  
RECT  
the ramp occurs at the valley of the C triangle waveform. When the  
capacitor determine the gain and time constant of the circuit. A  
differential error amplifier compares the voltage of C to an  
t
ramp voltage at C exceeds the voltage at the DC out pin in the DC  
P
RECT  
amplifier, the capacitor connected to C is discharged. The period  
internal reference of 2/7 V  
and adjusts the half-bridge oscillator  
P
REF  
of the PFC gate drive pulse correspond to the C ramp time. The  
maximum duty cycle, soft start function, and half-bridge off time are  
all controlled by the external capacitor and resistors connected to  
frequency so that the error voltage is minimized. This forces the  
average lamp current to be a constant.  
P
Dimming  
the D  
pin.  
MAX  
Dimming input should be an extra current put into charging C in  
3
Over Current Protection  
An over current is sensed by an external resistor connected to the  
current sense input pin, CSl. A voltage of minus 500mV at CSl  
addition to the current from Pin 7. This creates the same condition  
as higher voltage differential across Pins 8 and 9, hence, the IC  
reacts as if there is too much power applied to the lamps.  
3
1996 May 21  

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