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NCP1231D65R2G

更新时间： 2024-11-29 04:37:59
品牌 Logo 应用领域
安森美 - ONSEMI 控制器
页数 文件大小 规格书
21页 493K
描述
Low−Standby Power High Performance PWM Controller

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中文翻译

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NCP1231D65R2G 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：LEAD FREE, SOIC-8
针数：8Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.84模拟集成电路 - 其他类型：SWITCHING CONTROLLER
控制模式：CURRENT-MODE控制技术：PULSE WIDTH MODULATION
最大输入电压：18 V最小输入电压：8.4 V
标称输入电压：13 VJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：3功能数量：1
端子数量：8最高工作温度：125 °C
最低工作温度：-40 °C最大输出电流：1 A
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.75 mm表面贴装：YES
切换器配置：SINGLE最大切换频率：69 kHz
温度等级：AUTOMOTIVE端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

NCP1231D65R2G 数据手册

 浏览型号NCP1231D65R2G的Datasheet PDF文件第2页浏览型号NCP1231D65R2G的Datasheet PDF文件第3页浏览型号NCP1231D65R2G的Datasheet PDF文件第4页浏览型号NCP1231D65R2G的Datasheet PDF文件第5页浏览型号NCP1231D65R2G的Datasheet PDF文件第6页浏览型号NCP1231D65R2G的Datasheet PDF文件第7页 
NCP1231  
Low−Standby Power High  
Performance PWM  
Controller  
The NCP1231 represents a major leap towards achieving low  
standby power in medium−to−high power Switched−Mode Power  
Supplies such as notebook adapters, off−line battery chargers and  
consumer electronics equipment. Housed in SOIC−8 or PDIP−8, the  
NCP1231 contains all needed control functionality to build a rugged  
and efficient power supply. Among the unique features offered by the  
NCP1231 is an event management scheme that can disable the  
front−end PFC circuit during standby, thus reducing the no load power  
consumption. The NCP1231 itself goes into cycle skipping at light  
loads while limiting peak current (to 25% of nominal peak) so that no  
acoustic noise is generated and while in the skip cycle mode.  
http://onsemi.com  
MARKING  
DIAGRAMS  
8
231Dx  
y
ALYW  
G
SOIC−8  
D SUFFIX  
CASE 751  
1
1
The NCP1231 also features an internal latching function that can be  
used for Overvoltage Protection (OVP). The latch is triggered when  
the voltage on Pin 8 rises above 4.0 V. During an OVP condition, the  
output drive pulses are immediately stopped and the NCP1231 stays in  
8
1
1231Pzz  
AWL  
YYWWG  
PDIP−8  
P SUFFIX  
CASE 626  
the latched off condition until V drops below 4.0 V (V  
). In  
CCreset  
CC  
addition, Pin 8 also serves as a Brown−Out input which provides the  
necessary safety feature when the SMPS faces low mains situations.  
1
Features  
• Current−Mode Operation with Internal Ramp Compensation  
• Extremely Low Startup Current of 30 ꢀ A Typical  
• Skip−Cycle Capability at Low Peak Currents  
• Adjustable Soft−Start  
231Dxy = Device Code  
x = 1 or 6  
y = 0 or 3  
1231Pzz = Device Code  
zz = 65, 100 or 133  
= Assembly Location  
A
• Overvoltage and Brown−Out Protection  
L, WL  
Y, YY  
= Wafer Lot  
= Year  
• Short−Circuit Protection Independent of Auxiliary Level  
• Internal Frequency Dithering for Improved EMI Signature  
• Go−To−Standby Signal for PFC Front Stage  
• Extremely Low No−Load, Noiseless, Standby Power  
• Internal Leading Edge Blanking  
W, WW = Work Week  
G or G  
= Pb−Free Package  
PIN CONNECTIONS  
• +500 mA/−800 mA Peak Current Drive Capability  
• Available in Three Frequency Options: 65 kHz, 100 kHz, and 133 kHz  
• Direct Optocoupler Connection  
• SPICE Models Available for TRANsient and AC Analysis  
• Pb−Free Packages are Available  
1
8
PFC_V  
BO/OVP  
SS  
CC  
FB  
CS  
GND  
V
CC  
DRV  
Typical Applications  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 19 of this data sheet.  
• High Power AC−DC Adapters for Notebooks, etc.  
• Offline Battery Chargers  
• Set−Top Boxes Power Supplies, TV, Monitors, etc.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
July, 2006 − Rev. 4  
NCP1231/D  
1234567...21

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