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NC7WP02L8X PDF预览

NC7WP02L8X

更新时间: 2023-09-03 20:32:00
品牌 Logo 应用领域
安森美 - ONSEMI 逻辑集成电路
页数 文件大小 规格书
11页 323K
描述
TinyLogic ULP 双 2 输入 NOR 门极

NC7WP02L8X 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:VSON, LCC8,.06SQ,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.39
系列:PJESD-30 代码:S-XDSO-N8
JESD-609代码:e4长度:1.6 mm
负载电容(CL):30 pF逻辑集成电路类型:NOR GATE
最大I(ol):0.0005 A湿度敏感等级:1
功能数量:2输入次数:2
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:VSON封装等效代码:LCC8,.06SQ,20
封装形状:SQUARE封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.2/3.3 VProp。Delay @ Nom-Sup:43 ns
传播延迟(tpd):43 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:0.55 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):0.9 V标称供电电压 (Vsup):1.2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.6 mmBase Number Matches:1

NC7WP02L8X 数据手册

 浏览型号NC7WP02L8X的Datasheet PDF文件第1页浏览型号NC7WP02L8X的Datasheet PDF文件第3页浏览型号NC7WP02L8X的Datasheet PDF文件第4页浏览型号NC7WP02L8X的Datasheet PDF文件第5页浏览型号NC7WP02L8X的Datasheet PDF文件第6页浏览型号NC7WP02L8X的Datasheet PDF文件第7页 
October 2003  
Revised January 2005  
NC7WP02  
TinyLogic ULP Dual 2-Input NOR Gate  
General Description  
Features  
Space saving US8 package  
The NC7WP02 is  
a
dual 2-Input NOR Gate from  
Fairchild’s Ultra Low Power (ULP) series of TinyLogic  
Ideal for applications where battery life is critical, this prod-  
uct is designed for ultra low power consumption within the  
.
Ultra small MicroPak Pb-Free package  
0.9V to 3.6V VCC supply operation  
3.6V overvoltage tolerant I/O’s at VCC from 0.9V to 3.6V  
tPD  
V
CC operating range of 0.9V to 3.6V VCC.  
The internal circuit is composed of a minimum of inverter  
stages, including the output buffer, to enable ultra low static  
and dynamic power.  
3 ns typ for 3.0V to 3.6V VCC  
4 ns typ for 2.3V to 2.7V VCC  
The NC7WP02 is designed for optimized power and  
speed, and is fabricated with an advanced CMOS technol-  
ogy to achieve high speed operation while maintaining  
extremely low CMOS power dissipation.  
5 ns typ for 1.65V to 1.95V VCC  
6 ns typ for 1.40V to 1.60V VCC  
9 ns typ for 1.10V to 1.30V VCC  
24 ns typ for 0.90V VCC  
Power-Off high impedance inputs and outputs  
Static Drive (IOH/IOL  
)
±2.6 mA @ 3.00V VCC  
±2.1 mA @ 2.30V VCC  
±1.5 mA @ 1.65V VCC  
±1.0 mA @ 1.40V VCC  
±0.5 mA @ 1.10V VCC  
±20 µA @ 0.9V VCC  
Low noise switching using design techniques of  
Quiet Series noise/EMI reduction circuitry  
Ultra low dynamic power  
Ordering Code:  
Product  
Order Number Package  
Code  
Package Description  
Supplied As  
Number Top Mark  
NC7WP02K8X  
NC7WP02L8X  
MAB08A  
MAC08A  
WP02 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel  
Y4  
Pb-Free 8-Lead MicroPak, 1.6 mm Wide  
5k Units on Tape and Reel  
Pb-Free package per JEDEC J-STD-020B.  
Battery Life vs. V Supply Voltage  
CC  
TinyLogic ULP and ULP-A with up to 50% less power consumption can  
extend your battery life significantly.  
Battery Life = (Vbattery *Ibattery*.9)/(Pdevice)/24hrs/day  
Where, Pdevice = (ICC * VCC) + (CPD + CL) * VCC2 * f  
Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and  
derated 90% and device frequency at 10MHz, with CL = 15 pF load  
TinyLogic is a registered trademark, and Quiet Series and MicroPak are trademarks of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
DS500811  
www.fairchildsemi.com  

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