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NC7SZ38P5 PDF预览

NC7SZ38P5

更新时间: 2024-01-13 21:09:58
品牌 Logo 应用领域
其他 - ETC
页数 文件大小 规格书
7页 82K
描述
Single 2-input NAND Gate

NC7SZ38P5 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:TSSOP, TSSOP5/6,.08
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.38
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G5
JESD-609代码:e3长度:2 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.024 A湿度敏感等级:1
功能数量:1输入次数:2
端子数量:5最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP5/6,.08封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:5.2 ns传播延迟(tpd):13.2 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.25 mm

NC7SZ38P5 数据手册

 浏览型号NC7SZ38P5的Datasheet PDF文件第2页浏览型号NC7SZ38P5的Datasheet PDF文件第3页浏览型号NC7SZ38P5的Datasheet PDF文件第4页浏览型号NC7SZ38P5的Datasheet PDF文件第5页浏览型号NC7SZ38P5的Datasheet PDF文件第6页浏览型号NC7SZ38P5的Datasheet PDF文件第7页 
October 1996  
Revised January 2001  
NC7SZ38  
TinyLogic UHS 2-Input NAND Gate (Open Drain Output)  
General Description  
Features  
Space saving SOT23 or SC70 5-lead package  
Open Drain output stage for OR tied applications  
Ultra High Speed; tPD 2.4 ns Typ into 50 pF at 5V VCC  
The NC7SZ38 is a single 2-Input NAND Gate with open  
drain output stage from Fairchild’s Ultra High Speed Series  
of TinyLogic . The device is fabricated with advanced  
CMOS technology to achieve ultra high speed with high  
output drive while maintaining low static power dissipation  
over a very broad VCC operating range. The device is  
High Output Sink Drive; 24 mA at 3V VCC  
Broad VCC Operating Range; 1.65V to 5.5V  
specified to operate over the 1.65V to 5.5V VCC range. The  
inputs and output are high impedance when VCC is 0V.  
Inputs tolerate voltages up to 6V independent of VCC oper-  
Matches the performance of LCX when operated at  
3.3V VCC  
Power down high impedance inputs/output  
ating voltage. The open drain output stage will tolerate volt-  
ages up to 6V independent of VCC when in the high  
Overvoltage Tolerant inputs facilitate 5V to 3V  
translation  
impedance state.  
Patented noise/EMI reduction circuitry implemented  
Ordering Code:  
Order  
Number  
Package  
Number  
MA05B  
Product Code  
Top Mark  
7Z38  
Package Description  
Supplied As  
NC7SZ38M5  
NC7SZ38M5X  
NC7SZ38P5  
NC7SZ38P5X  
5-Lead SOT23, JEDEC MO-178, 1.6mm  
5-Lead SOT23, JEDEC MO-178, 1.6mm  
250 Units on Tape and Reel  
3k Units on Tape and Reel  
MA05B  
7Z38  
MAA05A  
MAA05A  
Z38  
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 250 Units on Tape and Reel  
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3k Units on Tape and Reel  
Z38  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
(Top View)  
Pin Descriptions  
Function Table  
Pin Names  
Description  
Y = AB  
A, B  
Y
Inputs  
Output  
Inputs  
Output  
A
L
B
L
Y
*H  
*H  
*H  
L
L
H
L
H
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
*H = HIGH Impedance output state (Open Drain)  
TinyLogic is a trademark of Fairchild Semiconductor Corporation.  
© 2001 Fairchild Semiconductor Corporation  
DS012175  
www.fairchildsemi.com  

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