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NC7SZ175P6 PDF预览

NC7SZ175P6

更新时间: 2024-11-22 23:53:23
品牌 Logo 应用领域
其他 - ETC 触发器
页数 文件大小 规格书
7页 81K
描述
Single D-Type Flip-Flop

NC7SZ175P6 数据手册

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May 1998  
Revised January 2001  
NC7SZ175  
TinyLogic UHS D-Type Flip-Flop  
with Asynchronous Clear  
General Description  
Features  
Space saving SC70 6-lead package  
The NC7SZ175 is a single positive edge-triggered D-type  
CMOS Flip-Flop with Asynchronous Clear from Fairchild’s  
Ultra High Speed Series of TinyLogic in the space saving  
SC70 6-lead package. The device is fabricated with  
advanced CMOS technology to achieve ultra high speed  
with high output drive while maintaining low static power  
dissipation over a very broad VCC operating range. The  
Ultra High Speed; tPD 2.6 ns Typ into 50 pF at 5V VCC  
High Output Drive; ±24 mA at 3V VCC  
Broad VCC Operating Range; 1.65V to 5.5V  
Matches the performance of LCX when operated at  
3.3V VCC  
device is specified to operate over the 1.65V to 5.5V VCC  
Power down high impedance inputs/output  
range. The inputs and output are high impedance when  
Overvoltage tolerant inputs facilitate 5V to 3V translation  
Patented noise/EMI reduction circuitry implemented  
VCC is 0V. Inputs tolerate voltages up to 7V independent of  
VCC operating voltage. This single flip-flop will store the  
state of the D input that meets the setup and hold time  
requirements on the LOW-to-HIGH Clock (CP) transition. A  
LOW input to Clear sets the Q output to LOW level. The  
Clear input is independent of clock.  
Ordering Code:  
Order  
Number  
Package  
Number  
MAA06A  
MAA06A  
Product Code  
Top Mark  
Z75  
Package Description  
Supplied As  
NC7SZ175P6  
NC7SZ175P6X  
6-Lead SC70, EIAJ SC88, 1.25mm Wide 250 Units on Tape and Reel  
6-Lead SC70, EIAJ SC88, 1.25mm Wide 3k Units on Tape and Reel  
Z75  
Function Table  
Logic Symbol  
Inputs  
Output  
IEEE/IEC  
CP  
D
C
Q
L
L
H
X
X
H
H
H
L
H
Connection Diagrams  
Qn  
L
X
H = HIGH Logic Level  
L = LOW Logic Level  
Qn = No change in data  
X = Immaterial  
Z = HIGH Impedance  
Pin Descriptions  
(Top View)  
Pin Names  
Description  
D
Data Input  
Clock Pulse Input  
Pin One Orientation Diagram  
CP  
C
Q
Clear Input  
Flip-Flop Output  
AAA represents Product Code Top Mark - see ordering code  
Note: Orientation of Top Mark determines Pin One location. Read the top  
product code mark left to right, Pin One is the lower left pin (see diagram).  
TinyLogic is a trademark of Fairchild Semiconductor Corporation.  
© 2001 Fairchild Semiconductor Corporation  
DS500158  
www.fairchildsemi.com  

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