Datasheet > NB3N1900K

NB3N1900K

更新时间： 2024-02-26 19:26:42

品牌	Logo	应用领域
安森美 - ONSEMI		PC
页数	文件大小	规格书
21页	211K
描述
Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe

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NB3N1900K 数据手册

NB3N1900K

3.3V 100/133 MHz

Differential 1:19 HCSL

Clock ZDB/Fanout Buffer for

PCIe^[

www.onsemi.com

MARKING

Description

The NB3N1900K differential clock buffers are designed to work in

conjunction with a PCIe compliant source clock synthesizer to provide

point−to−point clocks to multiple agents. The device is capable of

DIAGRAM*

distributing the reference clocks for Intel QuickPath Interconnect

1 72

NB3N

1900K

(Intel QPI), PCIe Gen1, Gen2, Gen3. The NB3N1900K internal PLL is

optimized to support 100 MHz and 133 MHz frequency operation.

The NB3N1900K supports HCSL output levels.

QFN72

MN SUFFIX

CASE 485DK

AWLYYWWG

Features

NB3N1900K = Specific Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• Fixed Feedback Path for Lowest Input−to−Output Delay

• Eight Dedicated OE# Pins for Hardware Control of Outputs

• PLL Bypass Configurable for PLL or Fanout Operation

• Selectable PLL Bandwidth

• Spread Spectrum Compatible: Tracks Input Clock Spreading for Low

EMI

ORDERING INFORMATION

• SMBus Programmable Configurations

See detailed ordering and shipping information on page 20 of

this data sheet.

• 100 MHz and 133 MHz PLL Mode to Meet the Next Generation

PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter

• 2 Tri−Level Addresses Selection (Nine SMBUS Addresses)

• Cycle−to−Cycle Jitter: < 50 ps

• Output−to−Output Skew: < 65 ps

• Input−to−Output Delay: Fixed at 0 ps

• Input−to−Output Delay Variation: < 50 ps

• Phase Jitter: PCIe Gen3 < 1 ps rms

• Phase Jitter: QPI 9.6GB/s < 0.2 ps rms

• QFN 72−pin Package, 10 mm x 10 mm

• These are Pb−Free Devices

Publication Order Number:

July, 2016 − Rev. 4

NB3N1900K/D

12 3 4 5 6 7...21

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