Datasheet > NB3N121K

NB3N121K

更新时间： 2024-02-02 09:54:51

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
11页	136K
描述
Differential 1:21 Fanout Clock

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NB3N121K 数据手册

NB3N121K

3.3V Differential 1:21

Fanout Clock and Data

Driver with HCSL Outputs

Description

http://onsemi.com

The NB3N121K is a differential 1:21 Clock and Data fanout buffer

with High−speed Current Steering Logic (HCSL) outputs optimized

for ultra low propagation delay variation. The NB3N121K is designed

with HCSL PCI Express clock distribution and FBDIMM applications

in mind.

Inputs can directly accept differential LVPECL, HCSL, and LVDS

signals per Figures 7, 8, and 9. Single ended LVPECL, HCSL,

LVCMOS, or LVTTL levels are accepted with a proper external V

QFN−52

MN SUFFIX

CASE 485M

reference supply per Figures 4 and 10. Input pins incorporate separate

internal 50 W termination resistors allowing additional single ended

system interconnect flexibility.

Output drive current is set by connecting a 475 W resistor from

IREF (Pin 1) to GND per Figure 6. Outputs can also interface to

LVDS receivers when terminated per Figure 11.

The NB3N121K specifically guarantees low output–to–output

skew. Optimal design, layout, and processing minimize skew within a

device and from device to device. System designers can take

advantage of the NB3N121K’s performance to distribute low skew

clocks across the backplane or the motherboard.

MARKING DIAGRAM*

NB3N

121K

AWLYYWWG

= Assembly Site

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Features

• Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and

400 MHz

• 340 ps Typical Rise and Fall Times

*For additional marking information, refer to

Application Note AND8002/D.

• 800 ps Typical Propagation Delay

• 100 ps Max Within Device Skew

• 150 ps Max Device−to−Device Skew

VTCLK

• Dtpd 100 ps Maximum Propagation Delay Variation Per Each

Differential Pair

• 0.1 ps Typical RMS Additive Phase Jitter

CLK

• LVDS Output Levels Optional with Interface Termination

• Operating Range: V = 3.0 V to 3.6 V with GND = 0 V

Q19

• Typical HCSL Output Level (700 mV Peak−to−Peak)

• These are Pb−Free Devices

Q19

Q20

Applications

VTCLK

• Clock Distribution

• PCIe I, II, III

• Networking

IREF

Q20

GND

REF

• High End Computing

• Routers

Figure 1. Simplified Logic Diagram

End Products

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

• Servers

• FBDIMM Memory Card

Publication Order Number:

March, 2012 − Rev. 1

NB3N121K/D

12 3 4 5 6 7...11

中文翻译

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与NB3N121K相关器件

型号	品牌	获取价格	描述	数据表
NB3N121KMNG	ONSEMI	获取价格	Differential 1:21 Fanout Clock
NB3N121KMNR2G	ONSEMI	获取价格	Differential 1:21 Fanout Clock
NB3N1900K	ONSEMI	获取价格	Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe
NB3N1900K_16	ONSEMI	获取价格	Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe
NB3N1900K_17	ONSEMI	获取价格	3.3V 100/133 MHz Differential 1:19 HCSL
NB3N1900KMNG	ONSEMI	获取价格	Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe
NB3N1900KMNTWG	ONSEMI	获取价格	Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe
NB3N1900KMNTXG	ONSEMI	获取价格	Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe
NB3N200S	ONSEMI	获取价格	3.3 V Differential Multipoint Low Voltage M-LVDS Driver Receiver
NB3N200S_15	ONSEMI	获取价格	3.3 V Differential Multipoint Low Voltage M-LVDS Driver Receiver

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