Datasheet > NB3H60113GH2MTR2G

NB3H60113GH2MTR2G

更新时间： 2024-10-03 11:13:27

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
11页	367K
描述
3.3 V OmniClock Generator with Single Ended LVCMOS Output

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3.3 V OmniClock Generator

with Single Ended LVCMOS

Output

NB3H60113GH2

The NB3H60113GH2, which is a member of the OmniClock family,

is a low power PLL−based clock generator. The device accepts

a single ended LVCMOS reference clock as input. It generates one

single ended LVCMOS modulated output at CLKOUT. Two LVCMOS

spread select signals SS1% and SS0% select one of the four spread

spectrum options at the output. The device can be powered down using

the Power Down pin (PD#).

www.onsemi.com

WDFN8

CASE 511AT

Features

• Member of the OmniClock Family of Programmable Clock

Generators

MARKING DIAGRAM

• Operating Power Supply: 3.3 V 10%

• I/O Standards:

♦ Input: 100 MHz CLKIN

H2MG

♦ Output: 100 MHz Modulated CLKOUT (LVCMOS)

• Input Frequency Range:

♦ Reference Clock: 100 MHz (LVCMOS)

• Configurable Spread Spectrum Frequency Modulation Parameters

(Type, Deviation, Rate)

H2 = Specific Device Code

= Date Code

= Pb−Free Device

• Output Drive Current for Single Ended Output: 16 mA

• Power Saving Mode through Power Down Pin

(Note: Microdot may be in either location)

• Temperature Range −40°C to 85°C

• Packaged in 8−Pin WDFN

ORDERING INFORMATION

See detailed ordering and shipping information on page 9 of

this data sheet.

• These are Pb−Free Devices

Typical Applications

• Display (TV Wall)

VDD

PD#

Output Control

Crystal /Clock Control

Configuration

Memory

Output

Divider

CLKOUT

Frequency and SS

CMOS/

Diff Buffer

PLL Block

Phase

Detector

CLKIN

Clock Buffer/

Crystal

Oscillator

and AGC

Charge

Pump

VCO

SS1%

SS0%

SS%

Select

Feedback

Divider

GND

Figure 1. Simplified Block Diagram

Publication Order Number:

December, 2019 − Rev. 0

NB3H60113GH2/D

12 3 4 5 6 7...11

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