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N84C163WD45TG PDF预览

N84C163WD45TG

更新时间: 2022-02-26 10:49:54
品牌 Logo 应用领域
安森美 - ONSEMI 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
11页 98K
描述
Supervisory Circuits with I2C Serial CMOS EEPROM Precision Reset Controller

N84C163WD45TG 数据手册

 浏览型号N84C163WD45TG的Datasheet PDF文件第3页浏览型号N84C163WD45TG的Datasheet PDF文件第4页浏览型号N84C163WD45TG的Datasheet PDF文件第5页浏览型号N84C163WD45TG的Datasheet PDF文件第7页浏览型号N84C163WD45TG的Datasheet PDF文件第8页浏览型号N84C163WD45TG的Datasheet PDF文件第9页 
8TH B  
                                                                                                             
T
ACK  
N84C163  
Hardware Data Protection  
down) V or until V reaches the reset threshold  
TH  
CC  
The N84C163 is designed with the following hardware  
data protection features to provide a high degree of data  
integrity.  
(power up) V . Any attempt to access the  
TH  
internal EEPROM is not recognized and an ACK  
will not be sent on the SDA line when RESET or  
RESET is active.  
1. The N84C163 features a WP pin. When the WP  
pin is tied high the entire memory array becomes  
write protected (read only).  
Reset Threshold Voltage  
The N84C163 is offered with five reset threshold voltage  
ranges. They are 4.50 ÷ 4.75 V, 4.25 ÷ 4.50 V, 3.00 ÷ 3.15 V,  
2.85 ÷ 3.00 V and 2.55 ÷ 2.70 V.  
2. The V sense provides write protection when  
CC  
V
CC  
falls below the reset threshold value (V ).  
TH  
The V lock out inhibits writes to the serial  
CC  
EEPROM whenever V falls below (power  
CC  
t
t
t
F
HIGH  
R
t
t
LOW  
LOW  
SCL  
t
t
HD:DAT  
SU:STA  
t
t
t
t
HD:STA  
SU:DAT  
SU:STO  
SDA IN  
BUF  
t
AA  
t
DH  
SDA OUT  
Figure 2. Bus Timing  
SCL  
SDA  
BYTE n  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
ADDRESS  
Figure 3. Write Cycle Timing  
SDA  
SCL  
START BIT  
STOP BIT  
Figure 4. Start/Stop Timing  
www.onsemi.com  
6

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