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N82503 PDF预览

N82503

更新时间: 2024-11-20 22:29:15
品牌 Logo 应用领域
英特尔 - INTEL /
页数 文件大小 规格书
45页 556K
描述
DUAL SERIAL TRANSCEIVER (DST)

N82503 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:QCCJ,
针数:44Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.81
地址总线宽度:边界扫描:NO
最大时钟频率:20 MHz数据编码/解码方法:NRZ; BIPH-LEVEL(MANCHESTER)
最大数据传输速率:1.25 MBps外部数据总线宽度:
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
长度:16.6 mm低功率模式:YES
DMA 通道数量:I/O 线路数量:
串行 I/O 数:3端子数量:44
片上数据RAM宽度:最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER认证状态:Not Qualified
RAM(字数):0座面最大高度:4.57 mm
最大压摆率:75 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:16.6 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches:1

N82503 数据手册

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82503  
DUAL SERIAL TRANSCEIVER (DST)  
82503 PRODUCT FEATURE SET OVERVIEW  
Y
Y
Single Component Ethernet* Interface  
to Both 802.3 10BASE-T and AUI  
Diagnostic Loopback  
Y
Y
Y
Y
Y
Y
Reset, Low Power Modes  
Network Status Indicators  
Defeatable Jabber Timer  
User Test Modes  
Y
Y
Automatic or Manual Port Selection  
Manchester Encoder/Decoder and  
Clock Recovery  
Y
No Glue Interface to Industry-Standard  
LAN Controllers  
10 MHz Transmit Clock Generator  
Ð Intel 82586, 82590, 82593 and 82596  
Ð AMD 7990 (LANCE*)  
One Micron CHMOS** IV (Px48)  
Technology  
Ð National Semiconductor 8390 and  
83932 (SONIC*)  
Y
Single 5-V Supply  
Ð Western Digital 83C690  
Ð Fujitsu 86950 (Etherstar*)  
INTERFACE FEATURES  
TPE  
Y
AUI  
Y
Complies with 10BASE-T, IEEE Std.  
Complies with IEEE 802.3 AUI Standard  
Direct Interface to AUI Transformers  
On-Chip AUI Squelch  
802.3i-1990 for Twisted Pair Ethernet  
Selectable Polarity Switching  
Direct Interface to TPE Analog Filters  
On-Chip TPE Squelch  
Y
Y
Y
Y
Y
Y
Y
Defeatable Link Integrity (LI)  
l
Support of Cable Lengths 100m  
A block diagram of a typical application is shown in Figure 1. The 82503 Dual Serial Transceiver is a high-inte-  
gration CMOS device designed to simplify interfacing industry standard Ethernet LAN Controllers to IEEE  
802.3 local area network applications (10BASE5, 10BASE2, and 10BASE-T). The component supports both  
an attachment unit interface (AUI) and a Twisted Pair Ethernet interface (TPE). It allows OEMs to design a  
state-of-the-art media interface that is jumperless and fully automatic. The 82503 includes on-chip AUI and  
TPE drivers and receivers; it offers designers a cost-effective, integrated solution for interfacing LAN control-  
lers to the wire medium.  
**CHMOS is a patented process of Intel Corporation.  
*Ethernet is a registered trademark of Xerox Corporation.  
LANCE is a registered trademark of Advanced Micro Devices.  
Etherstar is a registered trademark of Fujitsu Electronics.  
Sonic is a registered trademark of National Semiconductor Corporation.  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
©
COPYRIGHT INTEL CORPORATION, 1996  
October 1995  
Order Number: 290421-004  

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