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N74F835D PDF预览

N74F835D

更新时间: 2024-11-26 22:54:35
品牌 Logo 应用领域
恩智浦 - NXP 移位寄存器复用器
页数 文件大小 规格书
6页 63K
描述
8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out

N74F835D 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:24
Reach Compliance Code:unknown风险等级:5.84
其他特性:MUXED LATCHED 'B'/STANDARD 'A' PARALLEL INPUTS计数方向:RIGHT
系列:F/FASTJESD-30 代码:R-PDSO-G24
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:PARALLEL IN SERIAL OUT位数:8
功能数量:1端子数量:24
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE最大电源电流(ICC):65 mA
传播延迟(tpd):10 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5 mm最小 fmax:100 MHz

N74F835D 数据手册

 浏览型号N74F835D的Datasheet PDF文件第2页浏览型号N74F835D的Datasheet PDF文件第3页浏览型号N74F835D的Datasheet PDF文件第4页浏览型号N74F835D的Datasheet PDF文件第5页浏览型号N74F835D的Datasheet PDF文件第6页 
Philips Semiconductors  
Product specification  
8-bit shift register with 2:1 mux-in,  
latched “B” inputs, and serial out  
74F835  
FEATURES  
PIN CONFIGURATION  
Specifically designed for Video applications  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
V
CC  
PE  
CP  
Combines the 74F373, two 74F157s, and the 74F166 functions in  
D3B  
D3A  
D2B  
D2A  
D1B  
D1A  
D0B  
one package  
3
D4A  
D4B  
D5A  
D5B  
D6A  
D6B  
D7A  
D7B  
Q7  
Interleaved loading with 2:1 mux  
Dual 8-bit parallel inputs  
Transparent latch on all “B” inputs  
Guaranteed serial shift frequency to 100MHz  
Expandable to 16-bits or more with serial input  
4
5
6
7
8
9
D0A  
DS  
DESCRIPTION  
10  
11  
The 74F835 is a high speed 8-bit parallel/serial-in, serial-out shift  
register whose parallel inputs have been connected to an internal  
octal two-to-one multiplexer with all the “B” inputs connected to an  
octal latch.  
SA/B  
LE  
GND 12  
SF01355  
This 24-pin part is specifically designed for video bit shifting, where  
interleaved loading is desired and parts count is critical. It is useful in  
any design where a 2:1 mux input with a transparent latch is  
needed.  
ORDERING INFORMATION  
COMMERCIAL RANGE  
= 5V ±10%,  
PACKAGE  
DRAWING  
NUMBER  
V
DESCRIPTION  
CC  
T
amb  
= 0°C to +70°C  
TYPICAL  
SUPPLY CURRENT  
(TOTAL)  
TYPE  
TYPICAL f  
MAX  
24-pin plastic  
Slim DIP (300 mil)  
N74F835N  
SOT222-1  
SOT137-1  
24-pin plastic SOL  
N74F835D  
74F835  
150MHz  
45mA  
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE  
PINS  
D0A – D7A  
D0B – D7B  
DS  
DESCRIPTION  
Parallel data inputs  
74F (U.L.) HIGH/LOW  
1.0/1.0  
LOAD VALUE HIGH/LOW  
20µA/0.6mA  
Latched Parallel data inputs  
Serial data input  
1.0/1.0  
20µA/0.6mA  
1.0/1.0  
20µA/0.6mA  
CP  
Shift Register Clock input (active rising edge)  
Mux Select  
1.0/1.0  
20µA/0.6mA  
SA/B  
1.0/1.0  
20µA/0.6mA  
LE  
Latch Enable input (for B inputs)  
Parallel Enable input  
1.0/1.0  
20µA/0.6mA  
PE  
1.0/1.0  
20µA/0.6mA  
Q7  
Output  
50/33  
1.0mA/20mA  
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.  
1
1990 Jan 08  
853–0615 99490  

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