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N02L163WN1AB1-55I PDF预览

N02L163WN1AB1-55I

更新时间: 2024-02-18 15:44:58
品牌 Logo 应用领域
NANOAMP 存储内存集成电路静态存储器
页数 文件大小 规格书
11页 264K
描述
2Mb Ultra-Low Power Asynchronous CMOS SRAM

N02L163WN1AB1-55I 技术参数

是否Rohs认证:符合生命周期:Contact Manufacturer
包装说明:FBGA, BGA48,6X8,30Reach Compliance Code:unknown
风险等级:5.8Is Samacsys:N
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B48内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
端子数量:48字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, FINE PITCH并行/串行:PARALLEL
电源:2.5/3 V认证状态:Not Qualified
最大待机电流:0.00001 A最小待机电流:1.8 V
子类别:SRAMs最大压摆率:0.016 mA
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
Base Number Matches:1

N02L163WN1AB1-55I 数据手册

 浏览型号N02L163WN1AB1-55I的Datasheet PDF文件第3页浏览型号N02L163WN1AB1-55I的Datasheet PDF文件第4页浏览型号N02L163WN1AB1-55I的Datasheet PDF文件第5页浏览型号N02L163WN1AB1-55I的Datasheet PDF文件第7页浏览型号N02L163WN1AB1-55I的Datasheet PDF文件第8页浏览型号N02L163WN1AB1-55I的Datasheet PDF文件第9页 
NanoAmp Solutions, Inc.  
Timing Test Conditions  
N02L163WN1A  
Item  
0.1VCC to 0.9 VCC  
Input Pulse Level  
Input Rise and Fall Time  
Input and Output Timing Reference Levels  
Output Load  
5ns  
0.5 VCC  
CL = 30pF  
-40 to +85 oC  
Operating Temperature  
Timing  
2.3 - 3.6 V  
2.7 - 3.6 V  
Item  
Symbol  
Units  
Min.  
Max.  
Min.  
Max.  
tRC  
tAA  
tCO  
tOE  
Read Cycle Time  
70  
55  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
70  
70  
35  
35  
55  
55  
30  
30  
Chip Enable to Valid Output  
Output Enable to Valid Output  
Byte Select to Valid Output  
Chip Enable to Low-Z output  
Output Enable to Low-Z Output  
Byte Select to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Byte Select Disable to High-Z Output  
Output Hold from Address Change  
Write Cycle Time  
t
LB, tUB  
tLZ  
10  
5
10  
5
tOLZ  
tLBZ, tUBZ  
tHZ  
10  
0
10  
0
20  
20  
20  
20  
20  
20  
tOHZ  
0
0
t
LBHZ, tUBHZ  
tOH  
0
0
10  
70  
50  
50  
50  
40  
0
10  
55  
40  
40  
40  
40  
0
tWC  
tCW  
Chip Enable to End of Write  
Address Valid to End of Write  
Byte Select to End of Write  
Write Pulse Width  
tAW  
tLBW, tUBW  
tWP  
tAS  
Address Setup Time  
tWR  
Write Recovery Time  
0
0
tWHZ  
tDW  
Write to High-Z Output  
20  
20  
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Low-Z Output  
40  
0
35  
0
tDH  
tOW  
10  
10  
ns  
(DOC# 14-02-014 REV L ECN# 01-1000)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.  
6

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