Datasheet > N02L083WC2AN2

N02L083WC2AN2

更新时间： 2022-12-16 18:17:28

品牌	Logo	应用领域
NANOAMP		静态存储器
页数	文件大小	规格书
10页	223K
描述
2Mb Ultra-Low Power Asynchronous CMOS SRAM 256K x 8 bit

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

N02L083WC2AN2 数据手册

NanoAmp Solutions, Inc.

Functional Block Diagram

N02L083WC2A

Word

Address

Inputs

Address

Decode

Logic

A - A

Input/

Output

Mux

Page

16K Page

x 16 word

x 8 bit

Address

Inputs

Address

A - A

Decode

Logic

and

I/O - I/O

RAM Array

Buffers

CE1

CE2

Control

Logic

Functional Description

I/O₀- I/O₇

CE1

CE2

MODE

POWER

Standby¹

Write²

X²

High Z

Standby

Active

Data In

Data Out

High Z

Active

Read

Active

1. When the device is in standby mode, control inputs (WE and OE), address inputs and data input/outputs are internally isolated

from any external influence and disabled from exerting any influence externally.

2. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.

Capacitance

Item

Symbol

C_IN

Test Condition

Min

Max

Unit

V_IN= 0V, f = 1 MHz, T_A= 25^oC

Input Capacitance

I/O Capacitance

C_I/O

1. These parameters are verified in device characterization and are not 100% tested

(DOC# 14-02-015 REV E ECN# 01-0998)

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

123 4 5 6 7...10

下载PDF

与N02L083WC2AN2相关器件

型号	品牌	描述	获取价格	数据表
N02L083WC2AN2-55I	NANOAMP	Standard SRAM, 256KX8, 55ns, CMOS, PDSO32	获取价格
N02L083WC2AN-70I	NANOAMP	Standard SRAM, 256KX8, 70ns, CMOS, PDSO32	获取价格
N02L083WC2AT	NANOAMP	2Mb Ultra-Low Power Asynchronous CMOS SRAM 256K x 8 bit	获取价格
N02L083WC2AT2	NANOAMP	2Mb Ultra-Low Power Asynchronous CMOS SRAM 256K x 8 bit	获取价格
N02L083WC2AT2-70I	NANOAMP	Standard SRAM, 256KX8, 70ns, CMOS, PDSO32	获取价格
N02L083WC2AT-55I	NANOAMP	Standard SRAM, 256KX8, 55ns, CMOS, PDSO32	获取价格