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MXEI1480WB PDF预览

MXEI1480WB

更新时间: 2024-12-02 01:15:11
品牌 Logo 应用领域
IXYS /
页数 文件大小 规格书
2页 208K
描述
/-15V E Ink Source Driver

MXEI1480WB 数据手册

 浏览型号MXEI1480WB的Datasheet PDF文件第2页 
MXEI1480  
+/-15V E Ink Source Driver  
INTEGRATED  
C
IRCUITS  
D
IVISION  
Features  
Description  
CMOS Technology  
The MXEI1480 is a selectable 400 or 480 bit long,  
2-bit wide, serial-input parallel-output digital shift  
register with level conversion on each parallel output.  
+/-15 Volt Output Driver Supply Voltage  
Drives Segment or Active Matrix Displays  
4-Level Gray Scale  
The device converts the 2 digital bits into V  
, V  
,
POS  
SS  
25MHz Clock Frequency  
or V  
analog output voltages. An 8-bit input bus  
NEG  
Bidirectional Data Transfer  
Selectable Register Length  
2.7V to 5.5V Logic Supply Voltage  
Cascadable  
simultaneously inputs 4 groups of 2 bits each.  
The MXEI1480 consists of a selectable length  
Bidirectional Input Register, Transfer Latch, and 480  
bit Level Shifter / Output Driver. Each OUT pin is  
switched to one of [V , V  
the D0...D7 logic levels clocked into the MXEI1480,  
modified by the OE pin.  
, V  
] according to  
SS  
POS  
NEG  
Ordering Information  
Part  
Description  
The MXEI1480 is designed to operate over a  
MXEI1480WB  
MXEI1480WB  
MXEI1480TC  
Gold Bumped Die / Waffle Pack  
Gold Bumped Die / Wafer Form  
70mm Wide Tape Carrier  
temperature range of -40°C to +85°C, and is available  
as Gold Bumped Die in Waffle Pack, Gold Bumped  
Die in Wafer Form, and 70mm Wide Tape Carrier.  
Figure 1. Functional Block Diagram  
OUT1  
OUT2  
. . .  
OUT479 OUT480  
VPOS  
VSS  
LEVEL SHIFTER / DRIVER  
DECODE  
VNEG  
OE  
LE  
LATCH  
4-way Interleaved  
2-bit Register  
Stages  
4x(1 - 100)  
101-120  
480  
Data path when  
SHR = 1  
when  
SHR = 0  
mode 400  
Clock  
Direction  
D(7..0)  
CONTROL LOGIC  
SHR  
MODE  
CE  
CL  
PB-MXEI1480-January 21, 2014  
www.ixysic.com  
1

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