Datasheet > MWCT1015SAFVLLNFCR

MWCT1015SAFVLLNFCR

更新时间： 2024-11-18 08:56:39

品牌	Logo	应用领域
恩智浦 - NXP		微控制器
页数	文件大小	规格书
65页	1159K
描述
RISC Microcontroller

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MWCT1015SAFVLLNFCR 数据手册

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Document Number MWCT101xSF

NXP Semiconductors

Data Sheet: Advance Information

Rev. 2, 07/2018

MWCT101XSF

MWCT101XS Data Sheet

Key Features

• Memory and memory interfaces

– Up to 2 MB program flash memory with ECC

– 64 KB FlexNVM for data flash memory with ECC

and EEPROM emulation. Note: CSEc (Security) or

EEPROM writes/erase will trigger error flags in

HSRUN mode (112 MHz) because this use case is

not allowed to execute simultaneously. The device

will need to switch to RUN mode (80 MHz) to

execute CSEc (Security) or EEPROM writes/erase.

– Up to 256 KB SRAM with ECC

– Up to 4 KB of FlexRAM for use as SRAM or

EEPROM emulation

– Up to 4 KB Code cache to minimize performance

impact of memory access latencies

• Operating characteristics

– Voltage range: 2.7 V to 5.5 V

– Ambient temperature range: -40 °C to 105 °C for

HSRUN mode, -40 °C to 125 °C for RUN mode

• Arm™ Cortex-M4F core, 32-bit CPU

– Supports up to 112 MHz frequency (HSRUN) with

1.25 Dhrystone MIPS per MHz

– Arm Core based on the Armv7 Architecture and

Thumb®-2 ISA

– Integrated Digital Signal Processor (DSP)

– Configurable Nested Vectored Interrupt Controller

(NVIC)

– Single Precision Floating Point Unit (FPU)

– QuadSPI with HyperBus™ support

• Clock interfaces

• Mixed-signal analog

– 4 - 40 MHz fast external oscillator (SOSC)

– 48 MHz Fast Internal RC oscillator (FIRC)

– 8 MHz Slow Internal RC oscillator (SIRC)

– 128 kHz Low Power Oscillator (LPO)

– Up to 112 MHz (HSRUN) System Phased Lock

Loop (SPLL)

– Up to two 12-bit Analog-to-Digital Converter

(ADC) with up to 32 channel analog inputs per

module

– One Analog Comparator (CMP) with internal 8-bit

Digital to Analog Converter (DAC)

• Debug functionality

– Up to 50 MHz DC external square wave input clock

– Real Time Counter (RTC)

– Serial Wire JTAG Debug Port (SWJ-DP) combines

– Debug Watchpoint and Trace (DWT)

– Instrumentation Trace Macrocell (ITM)

– Test Port Interface Unit (TPIU)

• Power management

– Low-power Arm Cortex-M4F core with excellent

energy efficiency

– Flash Patch and Breakpoint (FPB) Unit

– Power Management Controller (PMC) with multiple

power modes: HSRUN, RUN, STOP, VLPR, and

VLPS. Note: CSEc (Security) or EEPROM writes/

erase will trigger error flags in HSRUN mode (112

MHz) because this use case is not allowed to

execute simultaneously. The device will need to

switch to RUN mode (80 Mhz) to execute CSEc

(Security) or EEPROM writes/erase.

• Human-machine interface (HMI)

– Up to 89 GPIO pins with interrupt functionality

– Non-Maskable Interrupt (NMI)

– Clock gating and low power operation supported on

specific peripherals.

This document contains information on a pre-production product. Specifications

and pre-production information herein are subject to change without notice.

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