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MU9C4480BF-90TBC PDF预览

MU9C4480BF-90TBC

更新时间: 2024-01-04 09:39:34
品牌 Logo 应用领域
MUSIC 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
32页 236K
描述
Content Addressable SRAM, 4KX64, 90ns, CMOS, PQFP64

MU9C4480BF-90TBC 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:QFP, QFP64,.6SQ,32Reach Compliance Code:unknown
风险等级:5.8最长访问时间:90 ns
JESD-30 代码:S-PQFP-G64内存密度:262144 bit
内存集成电路类型:CONTENT ADDRESSABLE SRAM内存宽度:64
湿度敏感等级:3端子数量:64
字数:4096 words字数代码:4000
最高工作温度:70 °C最低工作温度:
组织:4KX64封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP64,.6SQ,32
封装形状:SQUARE封装形式:FLATPACK
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.002 A子类别:SRAMs
最大压摆率:0.14 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
Base Number Matches:1

MU9C4480BF-90TBC 数据手册

 浏览型号MU9C4480BF-90TBC的Datasheet PDF文件第1页浏览型号MU9C4480BF-90TBC的Datasheet PDF文件第3页浏览型号MU9C4480BF-90TBC的Datasheet PDF文件第4页浏览型号MU9C4480BF-90TBC的Datasheet PDF文件第5页浏览型号MU9C4480BF-90TBC的Datasheet PDF文件第6页浏览型号MU9C4480BF-90TBC的Datasheet PDF文件第7页 
LANCAM B Family  
General Description  
GENERAL DESCRIPTION  
The LANCAM consists of various depths of 64-bit  
Content Addressable Memories (CAMs), with a 16-bit  
wide interface.  
the database. The ability to search data words up to 64 bits  
wide allows large address spaces to be searched rapidly  
and efficiently. A patented architecture links each CAM  
entry to associated data and makes this data available for  
use after a successful compare operation.  
CAMs, also known as associative memories, operate in the  
converse way to random access memories (RAM). In  
RAM, the input to the device is an address and the output  
is the data stored at that address. In CAM, the input is a  
data sample and the output is a flag to indicate a match and  
the address of the matching data. As a result, CAM  
searches large databases for matching data in a short,  
constant time period, no matter how many entries are in  
The MUSIC LANCAMs are ideal for address filtering and  
translation applications in LAN switches and routers. The  
LANCAMs are also well suited to encryption, database  
accelerators, and image processing.  
OPERATIONAL OVERVIEW  
To use the LANCAM, the user loads the data into the  
Comparand register, which is automatically compared to  
all valid CAM locations. The device then indicates  
whether or not one or more of the valid CAM locations  
contains data that matches the target data. The status of  
each CAM location is determined by two validity bits at  
each memory location. The two bits are encoded to render  
four validity conditions: Valid, Empty, Skip, and RAM,  
shown in Status Register Bits on page 24 (bits 29:28). The  
memory can be partitioned into CAM and associated  
RAM segments on 16-bit boundaries, but by using one of  
the two available Mask registers, the CAM/RAM  
partitioning can be set at any arbitrary size between zero  
and 64 bits.  
data to the Control, Comparand, and Mask registers  
automatically triggers a compare. Compares also may be  
initiated by a command to the device. Associated RAM  
data is available immediately after a successful compare  
operation. The Status register reports the results of  
compares including all flags and addresses. Two Mask  
registers are available and can be used in two different  
ways: to mask comparisons or to mask data writes. The  
RAM validity type allows additional masks to be stored in  
the CAM array where they may be retrieved rapidly.  
A simple four-wire control interface and commands  
loaded into the Instruction decoder control the device. A  
powerful instruction set increases the control flexibility  
and minimizes software overhead. Additionally, dedicated  
pins for match and multiple-match flags enhance  
performance when the device is controlled by a state  
machine. These and other features make the LANCAM a  
powerful associative memory that drastically reduces  
search delays.  
The LANCAM’s internal data path is 64 bits wide for  
rapid internal comparison and data movement. Vertical  
cascading of additional LANCAMs in a daisy chain  
fashion extends the CAM memory depth for large  
databases. Cascading requires no external logic. Loading  
2
Rev. 5.2  

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