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MU9C4480A-70DC PDF预览

MU9C4480A-70DC

更新时间： 2024-02-12 23:12:54
品牌 Logo 应用领域
MUSIC 存储内存集成电路静态存储器双倍数据速率局域网
页数 文件大小 规格书
32页 332K
描述
LANCAM A/L series

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MU9C4480A-70DC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Contact Manufacturer包装说明：QCCJ, LDCC44,.7SQ
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.8
Is Samacsys：N最长访问时间：52 ns
其他特性：BIT MASKING; LANCAMJESD-30 代码：S-PQCC-J44
JESD-609代码：e0内存密度：262144 bit
内存集成电路类型：CONTENT ADDRESSABLE SRAM内存宽度：64
湿度敏感等级：3功能数量：1
端子数量：44字数：4096 words
字数代码：4000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4KX64封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC44,.7SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
最大待机电流：0.007 A子类别：SRAMs
最大压摆率：0.2 mA最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

MU9C4480A-70DC 数据手册

 浏览型号MU9C4480A-70DC的Datasheet PDF文件第1页浏览型号MU9C4480A-70DC的Datasheet PDF文件第2页浏览型号MU9C4480A-70DC的Datasheet PDF文件第3页浏览型号MU9C4480A-70DC的Datasheet PDF文件第5页浏览型号MU9C4480A-70DC的Datasheet PDF文件第6页浏览型号MU9C4480A-70DC的Datasheet PDF文件第7页 
LANCAM A/L series (not recommended for new designs)  
Pin Descriptions  
/MI (Match Input, Input, TTL)  
/FI (Full Input, Input, TTL)  
The /MI input prioritizes devices in vertically cascaded  
systems. It is connected to the /MF output of the previous  
device in the daisy chain. The /MI pin on the first device in  
the chain must be tied HIGH.  
The /FI input generates a CAM-Memory-System-Full  
indication in vertically cascaded systems. It is connected  
to the /FF output of the previous device in the daisy chain.  
The /FI pin on the first device in a chain must be tied  
LOW.  
/MA (Device Match Flag, Output, TTL)  
/RESET (Reset, Input, TTL)  
The /MA output is LOW when one or more valid matches  
occur during the current or the last previous compare  
cycle. The /MA output is not qualified by /EC or /MI, and  
reflects the match flag from that specific device’s Status  
register. /MA is reset when the active register set is  
changed.  
/RESET must be driven LOW to place the device in a  
known state before operation, which resets the device to  
the conditions shown in Table 3 on page 11. The /RESET  
pin should be driven by TTL levels, not directly by an RC  
timeout. /E must be kept HIGH during /RESET.  
/MM (Device Multiple Match Flag, Output, TTL)  
The /MM output is LOW when more than one valid match  
occurs during the current or the last previous compare  
cycle. The /MM output is not qualified by /EC or /MI, and  
reflects the multiple match flag from that specific device’s  
Status register. /MM is reset when the active register set is  
changed.  
TEST1, TEST2 (Test, Input, TTL)  
These pins enable MUSIC production test modes that are  
not usable in an application. They should be connected to  
ground, either directly or through a pull-down resistor, or  
they may be left unconnected. These pins may not be  
implemented on all versions of these products.  
VCC, GND (Positive Power Supply, Ground)  
/FF (Full Flag, Output, TTL)  
These pins are the power supply connections to the  
LANCAM. VCC must meet the voltage supply  
requirements in the Operating Conditions section relative  
to the GND pins, which are at 0 volts (system reference  
potential), for correct operation of the device. All the  
ground and power pins must be connected to their  
respective planes with adequate bulk and high frequency  
bypassing capacitors in close proximity to the device.  
If enabled in the Control register, the /FF output goes  
LOW when no empty memory locations exist within the  
device (and in the daisy chain above the device as  
indicated by the /FI pin). The System Full flag is the /FF  
pin of the last device in the daisy chain, and the Next Free  
address resides in the device with /FI LOW and /FF  
HIGH. If disabled in the Control register, the /FF output  
only depends on the /FI input (/FF = /FI).  
4
Rev. 1  
1234567...32

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