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MU9C4480A-70DC

更新时间： 2024-01-27 23:31:38
品牌 Logo 应用领域
MUSIC 存储内存集成电路静态存储器双倍数据速率局域网
页数 文件大小 规格书
32页 332K
描述
LANCAM A/L series

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MU9C4480A-70DC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Contact Manufacturer包装说明：QCCJ, LDCC44,.7SQ
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.8
Is Samacsys：N最长访问时间：52 ns
其他特性：BIT MASKING; LANCAMJESD-30 代码：S-PQCC-J44
JESD-609代码：e0内存密度：262144 bit
内存集成电路类型：CONTENT ADDRESSABLE SRAM内存宽度：64
湿度敏感等级：3功能数量：1
端子数量：44字数：4096 words
字数代码：4000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4KX64封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC44,.7SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
最大待机电流：0.007 A子类别：SRAMs
最大压摆率：0.2 mA最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

MU9C4480A-70DC 数据手册

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Pin Descriptions  
LANCAM A/L series (not recommended for new designs)  
PIN DESCRIPTIONS  
Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.  
Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good  
layout and bypassing techniques. Refer to the DC Electrical Characteristics on page 26 for more information.  
/E (Chip Enable, Input, TTL)  
The /E input enables the device while LOW. The falling  
edge registers the control signals /W, /CM, and /EC. The  
rising edge locks the daisy chain, turns off the DQ pins,  
and clocks the Destination and Source Segment counters.  
The four cycle types enabled by /E are shown in Table 1.  
The /EC signal also enables the /MF–/MI daisy chain,  
which serves to select the device with the highest-priority  
match in a string of LANCAMs. Table 4 explains the  
effect of the /EC signal on a device with or without a  
match in both Standard and Enhanced modes. /EC must be  
HIGH during initialization.  
Table 1: I/O Cycles  
DQ15–0 (Data Bus, I/O, TTL)  
/W  
/CM  
LOW  
HIGH  
LOW  
HIGH  
Cycle Type  
The DQ15–0 lines convey data, commands, and status to  
and from the LANCAM. /W and /CM control the direction  
and nature of the information that flows to or from the  
device. When /E is HIGH, DQ15–0 go to HIGH-Z.  
LOW  
LOW  
HIGH  
HIGH  
Command Write Cycle  
Data Write Cycle  
Command Read Cycle  
Data Read Cycle  
/MF (Match Flag, Output, TTL)  
/W (Write Enable, Input, TTL)  
The /MF output goes LOW when one or more valid  
matches occur during a compare cycle. /MF becomes valid  
after /E goes HIGH on the cycle that enables the daisy  
chain (on the first cycle that /EC is registered LOW by the  
previous falling edge of /E; see Figure 8 on page 14). In a  
daisy chain, valid match(es) in higher priority devices are  
passed from the /MI input to /MF. If the daisy chain is  
enabled but the match flag is disabled in the Control  
register, the /MF output only depends on the /MI input of  
the device (/MF=/MI). /MF is HIGH if there is no match  
or when the daisy chain is disabled (/E goes HIGH when  
/EC was HIGH on the previous falling edge of /E). The  
System Match flag is the /MF pin of the last device in the  
daisy chain. /MF is reset when the active configuration  
register set is changed.  
The /W input selects the direction of data flow during a  
device cycle. /W LOW selects a Write cycle and /W HIGH  
selects a Read cycle.  
/CM (Data/Command Select, Input, TTL)  
The /CM input selects whether the input signals on  
DQ15–0 are data or commands. /CM LOW selects  
Command cycles and /CM HIGH selects Data cycles.  
/EC (Enable Daisy Chain, Input, TTL)  
The /EC signal performs two functions. The /EC input  
enables the /MF output to show the results of a  
comparison, as shown in Figure 8 on page 14. If /EC is  
LOW at the falling edge of /E in a given cycle, the /MF  
output is enabled. Otherwise, the /MF output is held  
HIGH.  
Figure 2: PLCC Pinout  
Rev. 1  
3
1234567...32

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