LIST-XL Family
Functional Description
FUNCTIONAL DESCRIPTION
The LIST-XL is a content-addressable memory (CAM) with
16-bitI/Ofornetworkaddressfilteringandtranslation,virtual
memory, data compression, caching, and table lookup
applications.ThememoryconsistsofstaticCAM,organized
in 64-bit data fields. Each data field can be partitioned into
a CAM and a RAM subfield on 16-bit boundaries. The
contents of the memory can be randomly accessed or
associatively accessed by the use of a compare. During
automaticcomparisoncycles,dataintheComparandregister
is automatically compared with the "Valid" entries in the
memory array. The Device ID can be read using a TCO PS
instruction (see Table 11 on page 16).
Data Movement (Read/Write)
Data can be moved from one of the data registers (CR, MR1,
or MR2) to a memory location that is based on the results of
the last comparison (Highest-Priority Match or Next Free),
or to an absolute address, or to the location pointed to by the
active Address register. Data also can be written directly to
the memory from the DQ bus using any of the above
addressing modes. The Address register may be directly
loaded and may be set to increment or decrement, allowing
DMA-type reading or writing from memory.
Configuration Register Sets
Two sets of configuration registers (Control, Segment
Control,Address,MaskRegister1,andPersistentSourceand
Destination) are provided to permit rapid context switching
betweenforegroundandbackgroundactivities.Writes,reads,
moves, and compares are controlled by the currently active
set of configuration registers. The foreground set would
typicallybepre-loadedwithvaluesusefulforcomparinginput
data, often called filtering, while the background set would
be pre-loaded with values useful for housekeeping activities
suchaspurgingoldentries.Movingfromtheforegroundtask
of filtering to the background task of purging can be done by
issuing a single instruction to change the current set of
configuration registers. The match condition of the device is
reset whenever the active register set is changed.
Data Input and Output Characteristics
The data inputs and outputs of the LIST-XL are multiplexed
fordataandinstructionsovera16-bitI/Obus.Internally,data
ishandledona64-bitbasis,sincetheComparandregister,the
mask registers, and each memory entry are 64 bits wide.
Memory entries are globally configurable into CAM and
RAM segments on 16-bit boundaries, as described in US
Patent5,383,146assignedtoMUSICSemiconductors.Seven
differentCAM/RAMsplitsarepossible,withtheCAMwidth
going from one to four segments, and the remaining RAM
width going from threeto zero segments. Finerresolution on
comparewidthispossiblebyinvokingamaskregisterduring
a compare, which does global masking on a bit basis. The
CAMsubfieldcontainstheassociativedata,whichentersinto
compares, while the RAM subfield contains the associated
data, which is not compared. In LAN bridges, the RAM
subfield could hold, for example, port-address and aging
information related to the destination or source address
information held in the CAM subfield of a given location. In
a translation application, the CAM field could hold the
dictionaryentries,whiletheRAMfieldholdsthetranslations,
with almost instantaneous response.
Control Register
The active Control register determines the operating
conditionswithinthedevice. Conditionssetbythisregister's
contents arereset, CAM/RAM partitioning, disable or select
maskingconditions, and disableor select auto-incrementing
or -decrementing the Address register. The active Segment
Control register contains separate counters to control the
writing of 16-bit data segments to the selected persistent
destination,andtocontrolthereadingof16-bitdatasegments
from the selected persistent source.
Validity Bits
Eachentryhastwovaliditybits(knownasSkipbitandEmpty
bit)associatedwithittodefineitsparticulartype:empty,valid,
skip, or RAM. When data iswritten to the active Comparand
register, and the active Segment Control register reaches its
terminal count, the contents of the Comparand register are
automaticallycomparedwiththeCAMportionofallthevalid
entries in the memory array. For added versatility, the
Comparand register can be barrel-shifted right or left one bit
at a time. A Compare instruction can then be used to force
another compare between the Comparand register and the
CAMportionofmemoryentriesofanyoneofthefourvalidity
types. After a Read or Move from Memory operation, the
validity bitsof the location read or moved will be copied into
the Status register, where they can be read from the Status
register using Command Read cycles.
4
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