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MU9C3640L-90TZI PDF预览

MU9C3640L-90TZI

更新时间： 2024-01-31 20:04:10
品牌 Logo 应用领域
MUSIC 存储内存集成电路静态存储器双倍数据速率
页数 文件大小 规格书
22页 185K
描述
LIST-XL Family

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MU9C3640L-90TZI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Contact Manufacturer零件包装代码：QFP
包装说明：QFP, QFP32,.35SQ,32针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.88
Is Samacsys：NJESD-30 代码：S-PQFP-G32
JESD-609代码：e0内存密度：16384 bit
内存集成电路类型：CONTENT ADDRESSABLE SRAM内存宽度：64
湿度敏感等级：3功能数量：1
端子数量：32字数：256 words
字数代码：256工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256X64封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP32,.35SQ,32
封装形状：SQUARE封装形式：FLATPACK
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
最大待机电流：0.002 A子类别：SRAMs
最大压摆率：0.03 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

MU9C3640L-90TZI 数据手册

 浏览型号MU9C3640L-90TZI的Datasheet PDF文件第1页浏览型号MU9C3640L-90TZI的Datasheet PDF文件第2页浏览型号MU9C3640L-90TZI的Datasheet PDF文件第4页浏览型号MU9C3640L-90TZI的Datasheet PDF文件第5页浏览型号MU9C3640L-90TZI的Datasheet PDF文件第6页浏览型号MU9C3640L-90TZI的Datasheet PDF文件第7页 
Pin Descriptions  
LIST-XL Family  
PIN DESCRIPTIONS  
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.  
Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the  
use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information.  
/E (Chip Enable, Input, TTL)  
/FF (Full Flag, Output, TTL)  
The/EinputenablesthedevicewhileLOW. Thefallingedge  
registersthecontrolsignals/Wand/CM.Therisingedgeturns  
off the DQ pins and clocks the Destination and Source  
Segment counters. The four cycle types enabled by /E are  
shown in Table 2 on page 2.  
The/FFoutputgoesLOWwhennoemptymemorylocations  
exist within the device.  
/RESET (Reset, Input, TTL)  
/RESET must be driven LOW to place the device in aknown  
state before operation, which will reset the device to the  
conditionsshowninTable4onpage8.The/RESETpinshould  
be driven by TTL levels, not directly by an RC time-out. /E  
must be kept HIGH during /RESET.  
/W (Write Enable, Input, TTL)  
The/Winputselectsthedirectionofdataflowduringadevice  
cycle. /W LOW selects a Write cycle and /W HIGH selects  
a Read cycle.  
VCC, GND (positive Power Supply, Ground)  
ThesepinsarethepowersupplyconnectionstotheLISTXL.  
VCC must meet the voltage supply requirements in the  
OperatingConditionssectionrelativetotheGNDpins,which  
are at 0 Volts (system reference potential), for correct  
operation of the device. All the ground and power pins must  
beconnectedtotheirrespectiveplaneswithadequatebulkand  
highfrequencybypassingcapacitorsincloseproximitytothe  
device.  
/CM (DATA/Command Select, Input, TTL)  
The /CM input selects whether the input signals on DQ15-0  
are data or commands. /CM LOW selects Command cycles  
and /CM HIGH selects Data cycles.  
/DQ15-0 (Data Bus, I/O, TTL)  
The DQ15-0 lines convey data, commands, and status to and  
from the LIST-XL. /W and /CM controls the direction and  
nature of the information that flows to or from the  
device.When /E is HIGH, DQ15-0 go to Hi-Z.  
/MF (Match Flag, Output, TTL)  
The /MF output goes LOW when one or more valid matches  
occur during the current or most recent compare cycle. /MF  
isHIGHifthereisnomatch./MFwillberesetwhentheactive  
configuration register set is changed.  
/MM (Device Multiple Match Flag, Output, TTL)  
The /MM output is LOW when more than one valid match  
occurs during the current or the most recent compare cycle.  
/MM will be reset when the active register set is changed.  
Rev. 3.1  
3
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