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MTP4N40EUA

更新时间: 2024-09-29 13:11:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 晶体晶体管功率场效应晶体管开关脉冲局域网
页数 文件大小 规格书
8页 242K
描述
Power Field-Effect Transistor, 4A I(D), 400V, 1.8ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-220AB

MTP4N40EUA 技术参数

生命周期:Obsolete包装说明:FLANGE MOUNT, R-PSFM-T3
Reach Compliance Code:unknown风险等级:5.69
Is Samacsys:N外壳连接:DRAIN
配置:SINGLE最小漏源击穿电压:400 V
最大漏极电流 (ID):4 A最大漏源导通电阻:1.8 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJEDEC-95代码:TO-220AB
JESD-30 代码:R-PSFM-T3元件数量:1
端子数量:3工作模式:ENHANCEMENT MODE
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:FLANGE MOUNT极性/信道类型:N-CHANNEL
功耗环境最大值:50 W认证状态:Not Qualified
表面贴装:NO端子形式:THROUGH-HOLE
端子位置:SINGLE晶体管元件材料:SILICON
Base Number Matches:1

MTP4N40EUA 数据手册

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Order this document  
by MTP4N40E/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
N–Channel Enhancement–Mode Silicon Gate  
TMOS POWER FET  
4.0 AMPERES  
400 VOLTS  
This high voltage MOSFET uses an advanced termination  
scheme to provide enhanced voltage–blocking capability without  
degrading performance over time. In addition, this advanced TMOS  
E–FET is designed to withstand high energy in the avalanche and  
commutation modes. The new energy efficient design also offers a  
drain–to–source diode with a fast recovery time. Designed for high  
voltage, high speed switching applications in power supplies,  
converters and PWM motor controls, these devices are particularly  
well suited for bridge circuits where diode speed and commutating  
safe operating areas are critical and offer additional safety margin  
against unexpected voltage transients.  
R
= 1.8 OHM  
DS(on)  
D
Robust High Voltage Termination  
Avalanche Energy Specified  
Source–to–Drain Diode Recovery Time Comparable to a Discrete  
Fast Recovery Diode  
G
Diode is Characterized for Use in Bridge Circuits  
S
I
and V Specified at Elevated Temperature  
DSS  
DS(on)  
CASE 221A–06, Style 5  
TO–220AB  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
400  
Unit  
Vdc  
Vdc  
Drain–to–Source Voltage  
V
DSS  
Drain–to–Gate Voltage (R  
GS  
= 1.0 M)  
V
DGR  
400  
Gate–to–Source Voltage — Continuous  
— Non–Repetitive (t 10 ms)  
V
± 20  
± 40  
Vdc  
Vpk  
GS  
V
GSM  
p
Drain Current — Continuous  
— Continuous @ 100°C  
— Single Pulse (t 10 µs)  
I
I
4.0  
3.0  
14  
Adc  
Apk  
D
D
I
p
DM  
Total Power Dissipation  
Derate above 25°C  
P
D
74  
0.59  
Watts  
W/°C  
Operating and Storage Temperature Range  
T , T  
J stg  
55 to 150  
°C  
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V = 10 Vdc, Peak I = 4.0 Apk, L = 25 mH, R = 25 )  
GS L G  
200  
Thermal Resistance — Junction to Case  
— Junction to Ambient  
R
R
1.7  
62.5  
°C/W  
°C  
θJC  
θJA  
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds  
T
260  
L
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
REV 2  
Motorola, Inc. 1996  

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