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MTD10N10ELT4G

更新时间： 2024-01-13 23:32:09
品牌 Logo 应用领域
安森美 - ONSEMI 晶体晶体管功率场效应晶体管
页数 文件大小 规格书
7页 79K
描述
TMOS E−FET Power Field Effect Transistor DPAK for Surface Mount

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MTD10N10ELT4G 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：LEAD FREE, CASE 369C-01, DPAK-3针数：3
Reach Compliance Code：not_compliantECCN代码：EAR99
风险等级：5.32其他特性：AVALANCHE RATED, LOGIC LEVEL COMPATIBLE
雪崩能效等级（Eas）：50 mJ外壳连接：DRAIN
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：100 V
最大漏极电流 (Abs) (ID)：10 A最大漏极电流 (ID)：10 A
最大漏源导通电阻：0.22 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：R-PSSO-G2JESD-609代码：e3
湿度敏感等级：1元件数量：1
端子数量：2工作模式：ENHANCEMENT MODE
最高工作温度：150 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260极性/信道类型：N-CHANNEL
最大功率耗散 (Abs)：40 W最大脉冲漏极电流 (IDM)：35 A
认证状态：Not Qualified子类别：FET General Purpose Powers
表面贴装：YES端子面层：Tin (Sn)
端子形式：GULL WING端子位置：SINGLE
处于峰值回流温度下的最长时间：40晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

MTD10N10ELT4G 数据手册

 浏览型号MTD10N10ELT4G的Datasheet PDF文件第2页浏览型号MTD10N10ELT4G的Datasheet PDF文件第3页浏览型号MTD10N10ELT4G的Datasheet PDF文件第4页浏览型号MTD10N10ELT4G的Datasheet PDF文件第5页浏览型号MTD10N10ELT4G的Datasheet PDF文件第6页浏览型号MTD10N10ELT4G的Datasheet PDF文件第7页 
MTD10N10EL  
TMOS E−FET™  
Power Field Effect Transistor  
DPAK for Surface Mount  
N−Channel Enhancement−Mode Silicon  
Gate  
http://onsemi.com  
This advanced TMOS E−FET is designed to withstand high energy  
in the avalanche and commutation modes. The new energy efficient  
design also offers a drain−to−source diode with a fast recovery time.  
Designed for low voltage, high speed switching applications in power  
supplies, converters and PWM motor controls, these devices are  
particularly well suited for bridge circuits where diode speed and  
commutating safe operating areas are critical and offer additional  
safety margin against unexpected voltage transients.  
R
TYP  
DS(ON)  
V
I MAX  
D
DSS  
100 V  
0.22 W  
10 A  
N−Channel  
D
Features  
• Avalanche Energy Specified  
• Source−to−Drain Diode Recovery Time Comparable to a Discrete  
G
Fast Recovery Diode  
• Diode is Characterized for Use in Bridge Circuits  
S
• I  
and V  
Specified at Elevated Temperature  
DSS  
DS(on)  
• Pb−Free Package is Available  
MARKING DIAGRAM & PIN ASSIGNMENTS  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Parameter  
Drain−to−Source Voltage  
Symbol Value  
Unit  
Vdc  
Vdc  
Gate 1  
4
V
100  
100  
DSS  
DGR  
YWW  
4
Drain−to−Gate Voltage (R = 1.0 MW)  
V
GS  
Drain 2  
10N  
Drain  
2
1
10ELG  
Gate−to−Source Voltage − Continuous  
V
15  
20  
Vdc  
Vpk  
GS  
3
Non−Repetitive (t ≤ 10 ms)  
V
DPAK  
CASE 369C  
p
GSM  
Source 3  
Drain Current − Continuous  
I
I
10  
6.0  
35  
Adc  
Apk  
D
D
(Surface Mount)  
STYLE 2  
− Continuous @ 100°C  
− Single Pulse (t ≤ 10 ms)  
I
p
DM  
Total Power Dissipation @ T = 25°C  
P
40  
0.32  
1.75  
W
W/°C  
W
C
D
Derate above 25°C  
10N10EL = Device Code  
Total Power Dissipation @ T = 25°C (Note 2)  
A
Y
WW  
G
= Year  
= Work Week  
= Pb−Free Package  
Operating and Storage Temperature Range  
Single Pulse Drain−to−Source Avalanche  
T , T  
−55 to  
150  
°C  
J
stg  
E
mJ  
AS  
Energy − Starting T = 25°C  
50  
J
(V = 25 Vdc, V = 5.0 Vdc, I = 10 Apk,  
DD  
GS  
L
ORDERING INFORMATION  
L = 1.0 mH, R = 25 W)  
G
†
Device  
Package  
Shipping  
Thermal Resistance  
− Junction−to−Case  
− Junction−to−Ambient (Note 1)  
− Junction−to−Ambient (Note 2)  
°C/W  
°C  
R
R
R
3.13  
100  
71.4  
θ
θ
θ
JC  
JA  
JA  
MTD10N10ELT4  
DPAK  
2500 Tape & Reel  
2500 Tape & Reel  
MTD10N10ELT4G  
DPAK  
(Pb−Free)  
Maximum Temperature for Soldering  
Purposes, 1/8″ from case for 10 sec  
T
260  
L
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. When surface mounted to an FR4 board using minimum recommended pad  
size.  
2. When surface mounted to an FR4 board using 0.5 sq in pad size.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 − Rev. 3  
MTD10N10EL/D  
 
1234567

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