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MT9171AN PDF预览

MT9171AN

更新时间: 2024-01-24 21:30:46
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信集成电路光电二极管综合业务数字网
页数 文件大小 规格书
25页 403K
描述
ISO2-CMOS ST-BUS FAMILY

MT9171AN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
数据速率:160 MbpsISDN访问速率:BASIC
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.505 mm湿度敏感等级:1
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
最小输出高电压:2.4 V最大输出低电流:0.005 A
最大输出低电压:0.4 V封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified参照点:S
座面最大高度:4.57 mm子类别:Digital Transmission Interfaces
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:DIGITAL SLIC
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:11.505 mm

MT9171AN 数据手册

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MT9171/72  
Advance Information  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
1
2
3
4
5
6
7
8
LOUT  
VBias  
VRef  
MS2  
MS1  
MS0  
VDD  
LIN  
TEST  
LOUT DIS  
Precan  
OSC1  
OSC2  
C4/TCK  
F0o/RCK  
DSTi/Di  
NC  
5
25  
24  
23  
22  
21  
20  
19  
MS2  
NC  
MS1  
MS0  
RegC  
LOUT DIS  
Precan  
OSC1  
OSC2  
NC  
6
7
RegC  
8
9
F0/CLD  
CDSTi/CDi  
CDSTo/CDo  
VSS  
10  
11  
9
10  
11  
F0/CLD  
NC  
C4/TCK  
DSTo/Do  
22 PIN PDIP  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
2
3
4
5
6
7
8
LOUT  
VDD  
LIN  
TEST  
LOUT DIS  
Precan  
OSC1  
NC  
VBias  
VRef  
MS2  
MS1  
MS0  
RegC  
NC  
28 PIN PLCC  
OSC2  
9
C4/TCK  
F0o/RCK  
DSTi/Di  
F0/CLD  
CDSTi/CDi  
CDSTo/CDo  
VSS  
10  
11  
12  
DSTo/Do  
24 PIN SSOP  
Figure 2 - Pin Connections  
Pin Description  
Pin #  
Name  
Description  
Line Out. Transmit Signal output (Analog). Referenced to VBias.  
22  
24  
28  
1
2
3
1
2
3
2
3
4
LOUT  
VBias  
VRef  
Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to VDD.  
Internal Reference Voltage output. Connect via 0.33 µF decoupling capacitor to  
VDD.  
4,5, 4,5,  
5,7, MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the  
6
7
8
6
7
9
8
various operating modes for a particular application. See Table 1 for the  
operating modes.  
9
RegC  
Regulator Control output (Digital). A 512 kHz clock used for switch mode power  
supplies. Unused in MAS/MOD mode and should be left open circuit.  
10  
F0/CLD Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative  
pulse input for the MASTER indicating the start of the active channel times of the  
device. Output for the SLAVE indicating the start of the active channel times of  
the device. Output in MOD mode providing a pulse indicating the start of the C-  
channel.  
9
10  
11  
12  
13  
CDSTi/ Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control  
CDi  
& signalling input in DN mode. In MOD mode this is a continuous bit stream at  
the bit rate selected.  
10  
CDSTo/ Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial  
CDo  
control & signalling output in DN mode. In MOD mode this is a continuous bit  
stream at the bit rate selected.  
11  
12  
12  
13  
14  
15  
VSS  
Negative Power Supply (0V).  
DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in  
DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.  
9-116  

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