Datasheet > MT8964AE

MT8964AE

更新时间： 2024-01-04 07:40:40

品牌	Logo	应用领域
MITEL		解码器编解码器电信集成电路光电二极管 PC
页数	文件大小	规格书
22页	327K
描述
Integrated PCM Filter Codec

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技术参数
数据手册

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MT8964AE 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Transferred	零件包装代码：	DIP
包装说明：	DIP, DIP18,.3	针数：	18
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.37	压伸定律：	MU-LAW
滤波器：	YES	最大增益公差：	0.25 dB
JESD-30 代码：	R-PDIP-T18	JESD-609代码：	e0
线性编码：	NOT AVAILABLE	负电源额定电压：	-5 V
功能数量：	1	端子数量：	18
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP18,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	+-5 V	认证状态：	Not Qualified
子类别：	Codecs	最大压摆率：	4 mA
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	电信集成电路类型：	PCM CODEC
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

MT8964AE 数据手册

ISO²-CMOS MT8960/61/62/63/64/65/66/67

External Control:

Powerdown

and 7 ( when both at logic high) of Register A

which in turn receives its control word input

via CSTi, when F1i is low and CA input is

either at V_EEor GNDD. Power is removed

from the filters and analog sections of the chip.

The analog ouput buffer at V_Rwill be

connected to GNDA. DSTo becomes high

impedance and the clocks to the majority of the

logic are stopped. SD outputs are unaffected

and may be updated as normal.

Powerdown of the chip is achieved in several ways:

Internal Control:

Initial Power-up. Initial application of V_DDand

_EEcauses powerdown for a period of 25 clock

cycles and during this period the chip will

accept input only from C2i. The B-register is

reset to zero forcing SD0-5 to be inactive. Bits

0-5 of Register A (gain adjust bits) are forced

to zero and bits 6 and 7 of Register A become

logic high thus reinforcing the powerdown.

CSTi Input. With CA at V_EEand CSTi held at

continuous logic high the chip assumes the

same state as described in External Control

(1) above.

Loss of C2i. Powerdown is entered 10 to 40

µs after C2i has assumed a continuous logic

high (V_DD). In this condition the chip will be in

the same state as in (1) above.

Note: If C2i stops at a continuous logic low

(GNDD), the digital data and status is

indeterminate.

Message

Waiting

-100V DC

MT8960/61/64/65

(With Relay

Drive)

From ST-BUS

Master Clock

to ST-BUS

CSTi

DSTi

C2i

GNDD

2.5V

-5V

Ref

GNDA

DSTo

2/4 Wire

Converter

Telephone

Line

0.1µF

Ring Trip

Filter

(With Relay

Drive)

ANUL

Gain

Section

Alignment

F1i

SD3

SD2

SD0

SD1

Ring Feed

-48V DC

(With Relay

Drive)

90V

RMS

Figure 7 - Typical Use of the Special Drive Outputs

6-27

1...6 7 8910 11 12...22

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