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MT8964AE PDF预览

MT8964AE

更新时间: 2024-02-27 08:58:44
品牌 Logo 应用领域
MITEL 解码器编解码器电信集成电路光电二极管PC
页数 文件大小 规格书
22页 327K
描述
Integrated PCM Filter Codec

MT8964AE 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:DIP
包装说明:DIP, DIP18,.3针数:18
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.37压伸定律:MU-LAW
滤波器:YES最大增益公差:0.25 dB
JESD-30 代码:R-PDIP-T18JESD-609代码:e0
线性编码:NOT AVAILABLE负电源额定电压:-5 V
功能数量:1端子数量:18
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP18,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:+-5 V认证状态:Not Qualified
子类别:Codecs最大压摆率:4 mA
标称供电电压:5 V表面贴装:NO
技术:CMOS电信集成电路类型:PCM CODEC
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MT8964AE 数据手册

 浏览型号MT8964AE的Datasheet PDF文件第4页浏览型号MT8964AE的Datasheet PDF文件第5页浏览型号MT8964AE的Datasheet PDF文件第6页浏览型号MT8964AE的Datasheet PDF文件第8页浏览型号MT8964AE的Datasheet PDF文件第9页浏览型号MT8964AE的Datasheet PDF文件第10页 
ISO2-CMOS MT8960/61/62/63/64/65/66/67  
Note: For Modes 1 and 2, F1i must be at logic low  
for one period of 3.9 µs, in each 125 µs cycle, when  
PCM data is being input and output, and the control  
word at CSTi enters Register A. For Mode 3, F1i  
must be at a logic low for two periods of 3.9 µs, in  
each 125 µs cycle. In the first period, CA must be at  
GNDD or VEE, and in the second period CA must be  
TRANSMIT (A/D)  
FILTER GAIN (dB)  
BIT 2  
BIT 1  
BIT 0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
+ 1  
+ 2  
+ 3  
+ 4  
+ 5  
+ 6  
+ 7  
high (VDD)  
.
Control Registers A, B  
The contents of these registers control the filter/  
codec functions as described in Tables 2 and 3.  
Bit 7 of the registers is the MSB and is defined as the  
first bit of the serial data stream input (corresponding  
to the sign bit of the PCM word).  
RECEIVE (D/A)  
FILTER GAIN (dB)  
BIT 5  
BIT 4  
BIT 3  
On initial power-up these registers are set to the  
powerdown condition for a maximum of 25 clock  
cycles. During this time it is impossible to change  
the data in these registers.  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
- 1  
- 2  
- 3  
- 4  
- 5  
- 6  
- 7  
Chip Testing  
By enabling Register B with valid data (eight-bit  
control word input to CSTi when F1i=GNDD and CA=  
VCC) the chip testing mode can be entered. Bits 6  
and 7 (most sign bits) define states for testing the  
transmit filter, receive filter and the codec function.  
The input in each case is VX input and the output in  
each case is VR output. (See Table 3 for details.)  
BIT 7  
BIT 6  
FUNCTION CONTROL  
0
0
1
1
0
1
0
1
Normal operation  
Digital Loopback  
Analog Loopback  
Powerdown  
Loopback  
Loopback of the filter/codec is controlled by the  
control word entered into Register A. Bits 6 and 7  
(most sign bits) provide either a digital or analog  
loopback condition. Digital loopback is defined as  
follows:  
Table 2. Control States - Register A  
PCM input data at DSTi is latched into the PCM  
input register and the output of this register is  
connected to the input of the 3-state PCM  
output register.  
Analog output buffer at VR has its input shorted  
to GNDA and disconnected from the receive  
filter output.  
Analog input at VX is disconnected from the  
transmit filter input.  
The digital input to the PCM digital-to-analog  
decoder is disconnected, forced to zero (0).  
The receive filter output is connected to the  
transmit filter input. Thus the decode signal is  
fed back through the receive path and encoded  
in the normal way. The analog output buffer at  
The output of the PCM encoder is disabled and  
thus the encoded data is lost. The PCM output  
at DSTo is determined by the PCM input data.  
V is not tested by this configuration.  
R
Analog loopback is defined as follows:  
PCM input data is latched, decoded and filtered  
as normal but not output at VR.  
In both cases of loopback, DSTi is the input  
and DSTo is the output.  
6-25  

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