MT8926
provides a two second output (register accessed)
and a one second output pin.
Functional Description
The MT8926 Performance Monitoring Adjunct Circuit
(PMAC) is designed to enable a MT8976/77 based
T1 interface to gather performance data and perform
maintenance functions as per ANSI T1.403 and
T1.408. Performance data collection includes CRC
errors, severely errored framing events, frame
synchronization-bit errors, line code violations, and
controlled slips. Maintenance functions include the
detection of alarms, SF line loopback code
generation and detection, ESF payload loopback, as
well as the transport of bit-oriented and message-
oriented signals over the Facility Data Link (FDL).
Two eight bit counters with overflow bits and resets
(resets counter and overflow bit) are provided to
record line code violations (BPV) and CRC errors.
The BPV counter will not count B8ZS encoding
violations. When either overflow bit goes high it will
generate a group two (G2) interrupt.
Two four bit counters are used to record framing
error events (FE) and severely errored framing
events (SE). The FE counter has an overflow
indication bit and can be cleared (resets counter and
overflow bit) by the user. Its overflow bit will generate
a group two (G2) interrupt when it goes high. A G2
interrupt will also be issued whenever the SE counter
is incremented.
The control and status data of the MT8926 is
transported over spare channels of the existing
MT8976/77 ST-BUS streams. Therefore, no new ST-
BUS streams are required to upgrade with the
PMAC.
The alarms that the PMAC monitors are alternate SF
yellow alarm (i.e., twelfth SF framing bit =1, ALRM),
ESF facility data link yellow alarm (RAI), loss of
signal (i.e., reception of 128 or more consecutive
zeros), and alarm indication signal (AIS, blue alarm
or all ones alarm). Therefore, the MT8926/MT8976/
77 combination supports a comprehensive alarm
package.
The PMAC has an on-board framer that uses the
received signal and extracted 8 kHz clock to achieve
synchronization. The result of this frame alignment is
logically ANDed with the SYN bit of the MT8976/77
CSTo stream to give FECV (see Table 5). This will
ensure that the PMAC can only declare
synchronization after the framer is synchronized.
The MT8926 will align to SF or ESF framing without
user selection.
The PMAC alarm registers and counters are updated
as the corresponding events occur. Once per frame
(8000 times a second) the state of these registers
and counters is recorded in a set of snap-shot
registers. This data in the snap-shot registers is then
inserted into the appropriate bit positions of the ST-
BUS status stream CSTo.
An interrupt (IRQ output) system is also provided to
reduce the requirement to monitor ST-BUS channels
continuously for exception conditions. Interrupt
sources are divided into group one (G1) for service
affecting events and group two (G2) for counter
overflows.
FDL bit-oriented messages can be communicated
via the PMAC transmit and receive bit-oriented
message registers. The user gains access to these
registers through the ST-BUS control streams. Valid
A timer has been included to allow scheduling of
T1.403/408 message-oriented performance reports
for transmission over the facility data link. This timer
bit-oriented messages consist of
a
series of
0-2
CSTi1 PCCW
2
3
X
4-6
7
8-10
11
12-14
15
16-18
PCCW
2
19 20-22 23 24-26 27 28-30 31
PCCW Tx PCCW PC PCCW LC
X
PCCW
2
X
PCCW
2
X
PCCW
2
X
2
BOM
2
W
2
W
T1
1-3
4-6
7-9
10-12
13-15
16-18
19-21
22-24
PMAC Control Word
Bit Function
Transmit Bit-Oriented
Message Register
Loopback Control
Word
7
6
5
4
3
2
1
0
SER
FER
Bit 1 Bit 0
Function
Normal
Payload Loopback
Bit
7
0
Function
Transmitted First
Transmitted Last
CRCR
BPVR
FSel
0
0
1
1
0
1
0
1
Line Loopback Enable Code (00001)
Line Loopback Disable Code (001)
8KEn
INTA
FDLEn
PCCW = Per Channel Control Word
FIgure 3 - CSTi1 Channel Allocation Versus T1 Channels
4-6
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