Datasheet > MT8926

MT8926

更新时间： 2024-02-15 13:48:34

品牌	Logo	应用领域
MITEL		监控
页数	文件大小	规格书
26页	312K
描述
ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monitoring Adjunct Circuit (PMAC)

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MT8926 技术参数

生命周期：	Obsolete	包装说明：	QCCJ,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e0	长度：	11.505 mm
功能数量：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	座面最大高度：	4.57 mm
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	11.505 mm
Base Number Matches：	1

MT8926 数据手册

MT8926

Pin Description (Continued)

Pin #

Name

Description

C2i

2.048 MHz Clock Input. This input accepts a 2.048 MHz clock signal, which is used to

clock ST-BUS control and data streams into and out of the PMAC. See Figures 13 and

14 for timing information.

System Ground.

Supply Voltage Input (+5 V).

RESET RESET Input. Must be high for normal operation. When low, the functions of the

MT8926 will be suspended.

FDLi

Facility Data Link Input. This input accepts a 4 kbit/sec. facility data link transmit

signal, which is routed back out transparently on FDLo if message-oriented signal

transmission is enabled (i.e., PMAC Control Word bit 0, FDLEn, is low). This signal is

not clocked into the PMAC. If bit-oriented messaging is enabled (FDLEn high), data on

this input will not be routed to FDLo (see pin 18, FDLo, below).

FDLo Facility Data Link Output. When bit-oriented messaging is enabled (i.e., PMAC

Control Word bit 0, FDLEn, is high), data in the Transmit BOM register will be appended

to a 1111 1111 (FF) flag and clocked out of the device at this output. The output timing

for this signal is shown in Figure 18. When bit-oriented messaging is disabled (FDLEn

low), data received at the FDLi pin is routed back out transparently on this pin (it is not

re-timed). See Figure 19 for timing information.

1SEC 1 Second Output. A one second timing signal derived from the ST-BUS F0i signal is

output on this pin. The output is low for 0.5 seconds and high for 0.5 seconds. It can be

used as an interrupt source to generate T1.403 message-oriented performance reports.

See Figure 16 for timing information.

IRQ

Interrupt Request Output. An open drain output that is to be externally connected to

through a pull-up resistor. The PMAC will pull this pin low to assert an interrupt

request. Interrupting events and their groupings are described in Tables 16 and 17. IRQ

is released by making bit 1 (Interrupt Acknowledge - INTA) of the PMAC Control Word

low. Once INTA is set, all interrupting signals of a particular group must be inactive

before the next interrupt of that group can assert IRQ. See Figure 17 for functional

timing information.

Internal Connection. Must be left open for normal operation.

System Ground.

DSTo

Internal Connection. Must be left open for normal operation.

Data ST-BUS Output. A 2.048 MBit/sec. serial output stream, which contains the 24

PCM or data channels to be transmitted on the T1 trunk. This data stream is

multiplexed from either input DSTi0 (Normal Mode) or input DSTi1 (Payload Loopback

Mode). The selection of either the Normal or Payload Loopback mode is made through

the Loopback Control Word. This output should be connected to DSTi of the MT8976/

77. When the loopback control word is set for line loopback code generation, the 24

PCM channels will contain the line loopback activate or deactivate code stream. See

Figure 14 for timing information.

DSTi0 Data ST-BUS Input 0. A 2.048 MBit/sec. serial input stream, which contains the 24

PCM or data channels to be transmitted on the T1 trunk in Normal Mode. This input

should be connected to the system side output stream.

DSTi1 Data ST-BUS Input 1. A 2.048 MBit/sec. serial input stream, which contains the 24

PCM or data channels to be transmitted on the T1 trunk in Payload Loopback Mode.

This input should be connected to DSTo of the MT8976/77.

Internal Connection. Must be tied to V for normal operation.

Supply Voltage Input (+5 V).

4-5

1 234 5 6 7...26

下载PDF

与MT8926相关器件

型号	品牌	描述	获取价格	数据表
MT8926AE	ZARLINK	Telecom Circuit, 1-Func, CMOS, PDIP28, PLASTIC, DIP-28	获取价格
MT8926AE	MITEL	ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monito	获取价格
MT8926AP	MITEL	ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monito	获取价格
MT8926AP	ZARLINK	Telecom Circuit, 1-Func, CMOS, PQCC28, PLASTIC, LCC-28	获取价格
MT8926APR	MICROSEMI	SPECIALTY TELECOM CIRCUIT, PQCC28, PLASTIC, LCC-28	获取价格
MT8926APR	ZARLINK	Telecom Circuit, 1-Func, CMOS, PQCC28, PLASTIC, LCC-28	获取价格

与MT8926相关文章

STM32F030C6芯片介绍：主要参数分析、引脚配置说明、功耗及封装
2024-05-11

10
PCF8591数据手册解读：参数、引脚说明
2024-05-11

17
一文带你了解ss8050参数、引脚配置、应用指南
2024-05-11

7
深入解析AD7606高性能多通道模数转换器：资料手册参数分析
2024-05-10

11

产品中心

服务支持

精选活动

关于我们

帮助中心

MT8926

MT8926 技术参数

MT8926 数据手册

与MT8926相关器件

与MT8926相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MT8926

MT8926 技术参数

MT8926 数据手册

与MT8926相关器件

与MT8926相关文章

您还可以找

您在本页遇到什么问题？