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MT8926

更新时间： 2024-01-03 17:41:46
品牌 Logo 应用领域
MITEL 监控
页数 文件大小 规格书
26页 312K
描述
ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monitoring Adjunct Circuit (PMAC)

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MT8926 技术参数

生命周期：Obsolete包装说明：QCCJ,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84JESD-30 代码：S-PQCC-J28
JESD-609代码：e0长度：11.505 mm
功能数量：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
认证状态：Not Qualified座面最大高度：4.57 mm
标称供电电压：5 V表面贴装：YES
技术：CMOS电信集成电路类型：TELECOM CIRCUIT
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：11.505 mm
Base Number Matches：1

MT8926 数据手册

 浏览型号MT8926的Datasheet PDF文件第1页浏览型号MT8926的Datasheet PDF文件第3页浏览型号MT8926的Datasheet PDF文件第4页浏览型号MT8926的Datasheet PDF文件第5页浏览型号MT8926的Datasheet PDF文件第6页浏览型号MT8926的Datasheet PDF文件第7页 
MT8926  
1
2
3
4
5
VSS  
ECLK  
RxA  
RxB  
IC  
E8Ki  
E8Ko  
VSS  
CSTo  
CSTi0  
CSTi1  
F0i  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VDD  
IC  
DSTi1  
DSTi0  
DSTo  
IC  
VSS  
IC  
IRQ  
1SEC  
FDLo  
FLDi  
RESET  
VDD  
4
5
6
7
3 2  
1
28 27 26  
25  
DSTi0  
DSTo  
IC  
VSS  
IC  
IRQ  
1SEC  
IC  
E8Ki  
24  
23  
22  
21  
E8Ko  
6
7
8
9
10  
11  
VSS  
CSTo  
CSTi0  
8
9
10  
11  
20  
19  
CSTi1  
12 13 14 15 16 17 18  
12  
13  
14  
C2i  
VSS  
28 PIN PLASTIC DIP  
28 PIN PLASTIC J-LEAD  
Figure 2 - Pin Connections  
Pin Description  
Pin #  
Name  
Description  
1
2
V
System Ground.  
SS  
ECLK Extracted Clock Input. A 1.544 MHz clock derived from the received data. This signal is  
used to clock in the data on pins RxA and RxB.  
See Figure 11 for timing information.  
3
4
RxA  
RxB  
Receive A Input. A unipolar active low signal decoded from the received T1 signal. See  
Figure 11 for timing information.  
Receive B Input. A unipolar active low signal decoded from the received T1 signal. See  
Figure 11 for timing information.  
5
6
IC  
Internal Connection. Must be tied to V for normal operation.  
SS  
E8Ki  
Extracted 8 kHz Input. A low going pulse on this input is used by the PMAC to locate the  
framing bit in the received signal. The device uses this information to detect errors in the  
received framing bits. Connect to E8Ko of the MT8976/77. See Figure 12 for timing  
information.  
7
E8Ko 8 kHz clock output. The 8 kHz signal input at E8Ki is output on this pin when bit 2 (8KEn)  
of the PMAC Control Word is set. The output is pulled high when 8KEn is reset. See  
Figure 12 for timing information.  
8
9
V
System Ground.  
SS  
CSTo  
Control ST-BUS Output. The data that enters the PMAC on CSTi0 will exit the device on  
this pin. Data derived by the PMAC will be inserted into specific channels of this output  
stream. See Figures 13 and 14 for timing information and Figure 5 for channel allocation.  
10  
11  
12  
CSTi0 Control ST-BUS Input 0. Accepts the serial ST-BUS stream output on CSTo of the  
MT8976/77. The data that enters the PMAC on this pin exits the device on CSTo. The  
contents of specific CSTi0 channels is replaced by data derived by the PMAC. See Figures  
13 and 14 for timing information and Figure 4 for channel allocation.  
CSTi1 Control ST-BUS Input 1. Channel 11 of this ST-BUS input stream is used to control  
specific features in the device (Table 14). Channel 7 is used for the transmit bit-oriented  
message (Table 13), and channel 15 is used to control loopback functions (Table 4). See  
Figure 13 for timing information and Figure 3 for channel allocation.  
F0i  
Frame Pulse Input. This input accepts an 8 kHz signal, which is used to delineate the ST-  
BUS frame boundary. See Figure 15 for timing information.  
4-4  
1234567...26

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