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MT88L85AE1 PDF预览

MT88L85AE1

更新时间： 2024-01-30 09:40:38
品牌 Logo 应用领域
美高森美 - MICROSEMI 电信光电二极管电信集成电路
页数 文件大小 规格书
29页 665K
描述
DTMF Signaling Circuit, CMOS, PDIP24, 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-24

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MT88L85AE1 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：DIP,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.68
JESD-30 代码：R-PDIP-T24JESD-609代码：e3
长度：31.623 mm功能数量：1
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：5.334 mm
标称供电电压：3 V表面贴装：NO
技术：CMOS电信集成电路类型：DTMF SIGNALING CIRCUIT
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

MT88L85AE1 数据手册

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MT88L85  
3 V Integrated DTMF Transceiver with  
Power-Down and Adaptive Micro Interface  
Data Sheet  
August 2005  
Features  
•
•
•
Complete DTMF transmitter/receiver  
Low voltage operation (2.7-3.6 V)  
Ordering Information  
MT88L85AE  
24 Pin PDIP  
Tubes  
MT88L85AN  
MT88L85AP  
24 Pin SSOP  
28 Pin PLCC  
24 Pin SSOP  
24 Pin SSOP*  
24 Pin PDIP*  
24 Pin SSOP*  
Tubes  
Adaptive micro interface enables compatibility  
with Intel and Motorola processors  
DTMF transmitter/receiver power-down via  
register control or power-down pin  
Tubes  
MT88L85ANR  
MT88L85AN1  
MT88L85AE1  
MT88L85ANR1  
Tape & Reel  
Tubes  
•
Tubes  
Tape & Reel  
*Pb Free Matte Tin  
•
•
•
Adjustable guard time  
Automatic tone burst mode  
Call progress tone detection to -30 dBm  
-40°C to +85°C  
Description  
Applications  
The MT88L85 is a monolithic DTMF transceiver with  
call progress filter. It is fabricated in CMOS technology  
offering low power consumption and high reliability.  
•
•
•
•
•
•
Credit card systems  
Paging systems  
The receiver section is based upon the industry  
standard MT8870 DTMF receiver. The transmitter  
utilizes a switched capacitor D/A converter for low  
distortion, high accuracy DTMF signalling. Internal  
counters provide a burst mode such that tone bursts  
can be transmitted with precise timing. A call progress  
filter can be selected allowing a microprocessor to  
analyze call progress tones.  
Repeater systems/mobile radio  
Interconnect dialers  
Pay phones  
Remote monitor/Control systems  
D0  
Data  
Row and  
Column  
Counters  
D/A  
Transmit Data  
Bus  
D1  
D2  
D3  
∑
TONE  
Converters  
Register  
Buffer  
Status  
Interrupt  
Logic  
Tone Burst  
Gating Cct.  
Register  
Control  
Logic  
IRQ/CP  
Control  
Register  
A
IN+  
IN-  
GS  
+
-
Dial  
Tone  
Filter  
High Group  
Filter  
Digital  
Algorithm  
and Code  
Converter  
DS/RD  
CS  
Control  
Register  
B
I/O  
Control  
Low Group  
Filter  
OSC1  
OSC2  
Oscillator  
R/W/WR  
RS0  
Circuit  
Control  
Logic  
Receive Data  
Register  
Steering  
Logic  
Bias  
Circuit  
V
V
V
PWDN  
ESt  
St/GT  
DD Ref  
SS  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1999-2005, Zarlink Semiconductor Inc. All Rights Reserved.  
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