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MT5C2568LECW-70/883C PDF预览

MT5C2568LECW-70/883C

更新时间： 2024-02-14 09:03:39
品牌 Logo 应用领域
MICROSS 静态存储器内存集成电路
页数 文件大小 规格书
15页 324K
描述
Standard SRAM, 32KX8, 70ns, CMOS, CQCC32, CERAMIC, LCC-32

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MT5C2568LECW-70/883C 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFJ
包装说明：QCCN,针数：32
Reach Compliance Code：compliantECCN代码：3A001.A.2.C
HTS代码：8542.32.00.41风险等级：5.64
Is Samacsys：N最长访问时间：70 ns
JESD-30 代码：R-CQCC-N32JESD-609代码：e0
长度：13.97 mm内存密度：262144 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端子数量：32
字数：32768 words字数代码：32000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：32KX8
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified筛选级别：MIL-STD-883
座面最大高度：3.048 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：TIN LEAD
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：11.43 mmBase Number Matches：1

MT5C2568LECW-70/883C 数据手册

 浏览型号MT5C2568LECW-70/883C的Datasheet PDF文件第2页浏览型号MT5C2568LECW-70/883C的Datasheet PDF文件第3页浏览型号MT5C2568LECW-70/883C的Datasheet PDF文件第4页浏览型号MT5C2568LECW-70/883C的Datasheet PDF文件第5页浏览型号MT5C2568LECW-70/883C的Datasheet PDF文件第6页浏览型号MT5C2568LECW-70/883C的Datasheet PDF文件第7页 
SRAM  
MT5C2568  
Austin Semiconductor, Inc.  
32K x 8 SRAM  
PIN ASSIGNMENT  
(Top View)  
SRAM MEMORY ARRAY  
28-PIN SOJ (ECJ)  
28-Pin DIP (C, CW)  
32-Pin LCC (ECW)  
AVAILABLE AS MILITARY  
SPECIFICATIONS  
•SMD 5962-88662  
•MIL-STD-883  
VCC  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0 10  
DQ1 11  
DQ2 12  
DQ3 13  
1
2
3
4
5
6
7
8
9
28  
4
3 2 1 32 31 30  
27 WE\  
26 A13  
25 A8  
5
6
7
8
9
10  
11  
12  
13  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
NC  
DQ1  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A8  
A9  
A11  
NC  
OE\  
A10  
CE\  
DQ8  
DQ7  
24 A9  
23 A11  
22 OE\  
21 A10  
20 CE\  
19 DQ8  
18 DQ7  
17 DQ6  
16 DQ5  
15 DQ4  
FEATURES  
• Access Times: 12, 15, 20, 25, 35, 45, 55, 70, & 100ns  
• Battery Backup: 2V data retention  
• Low power standby  
• High-performance, low-power CMOS double-metal process  
• Single +5V (+10%) Power Supply  
• Easy memory expansion with CE\  
• All inputs and outputs are TTL compatible  
14 15 16 17 18 19 20  
VSS  
14  
28-Pin LCC (EC)  
OPTIONS  
• Timing  
MARKING  
3
2 1 28 27  
28-Pin Flat Pack (F)  
12ns access1  
15ns access1  
20ns access  
25ns access  
35ns access  
45ns access  
55ns access2  
70ns access2  
100ns access  
-12  
-15  
-20  
-25  
-35  
-45  
-55  
-70  
-1004  
4
5
6
7
8
A6  
A5  
A4  
A3  
A2  
A1  
A0  
DQ1  
DQ2  
26  
25  
24  
23  
22  
21  
20  
19  
18  
A13  
A8  
A9  
A11  
OE\  
A10  
CE\  
DQ8  
DQ7  
VCC  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0 10  
DQ1 11  
DQ2 12  
DQ3 13  
1
2
3
4
5
6
7
8
9
28  
27 WE\  
26 A13  
25 A8  
24 A9  
9
23 A11  
22 OE\  
21 A10  
20 CE\  
19 DQ8  
18 DQ7  
17 DQ6  
16 DQ5  
15 DQ4  
10  
11  
12  
13 14 15 16 17  
VSS  
14  
• Package(s)3  
Ceramic DIP (300 mil)  
Ceramic DIP (600 mil)  
Ceramic LCC (28 leads)  
Ceramic LCC (32 leads)  
Ceramic Flat Pack  
Ceramic SOJ  
C
No. 108  
GENERAL DESCRIPTION  
CW  
EC  
ECW  
F
No. 110  
No. 204  
No. 208  
No. 302  
No. 500  
The Austin Semiconductor SRAM family employs  
high-speed, low power CMOS designs using a four-transistor  
memory cell. These SRAMs are fabricated using double-layer  
metal, double-layer polysilicon technology.  
ECJ  
For flexibility in high-speed memory applications, Aus-  
tin Semiconductor offers chip enable (CE\) and output enable  
(OE\) capability. These enhancements can place the outputs in  
High-Z for additional flexibility in system design.  
• Operating Temperature Ranges  
Military -55oC to +125oC  
Industrial -40oC to +85oC  
XT  
IT  
Writing to these devices is accomplished when write  
enable (WE\) and CE\ inputs are both LOW. Reading is accom-  
plished when WE\ remains HIGH and CE\ and OE\ go LOW.  
The device offers a reduced power standby mode when dis-  
abled. This allows system designs to achieve low standby  
power requirements.  
The “L” version provides a battery backup/low volt-  
age data retention mode, offering 2mW maximum power dissi-  
pation at 2 volts. All devices operate from a single +5V power  
supply and all inputs and outputs are fully TTL compatible.  
• 2V data retention/low power  
L
NOTES:  
1. -12 and -15 available in IT only.  
2. Electrical characteristics identical to those provided for the  
45ns access devices.  
3. Plastic SOJ (DJ Package) is available on the AS5C2568 datasheet.  
4. Available in CW, ECW, and F packages only.  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2568  
Rev. 1.0 9/99  
1
1234567...15

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