‡
ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
SYNCFLASH®
MEMORY
MT28S4M16B1LL – 1 Meg x 16 x 4 banks
MT28S2M32B1LL – 512K x 32 x 4 banks
FEATURES
• 125 MHz SDRAM-compatible read timing
• Fully synchronous; all signals registered on
positive edge of system clock
PINASSIGNMENT(TopView)
90-Ball FBGA – 2 Meg x 32
1
2
3
7
8
9
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access
• Programmable burst lengths:
DQ26
DQ24
V
SS
Vcc
DQ23
DQ21
A
B
C
D
E
DQ28
VccQ
DQ27
DQ29
DQ31
DQM3
A5
V
SS
Q
VccQ
DQ22
DQ17
NC
V
SSQ
DQ19
VccQ
VccQ
VssQ
Vcc
V
V
SS
Q
Q
DQ25
DQ30
NC
DQ20
DQ18
DQ16
DQM2
A0
1, 2 , 4, 8, or full page (read)
1, 2, 4, or 8 (write)
SS
VccQ
• LVTTL-compatible inputs and outputs
• 3.0V–3.6V VCC, 1.65V–1.95V VCCQ
Additional VHH hardware protect mode (RP#)
• Supports CAS latency of 1, 2, and 3
• Four-bank architecture supports true concurrent
operation with zero latency
Read any bank while programming or erasing
any other bank
• Deep power-down mode: 50µA (MAX)
• Cross-compatible Flash memory command set
• Operating temperature range of -40oC to +85oC
V
SS
A3
A2
F
A4
A7
A6
A10
NC
A1
G
H
J
A8
VccP
A9
BA1
NC
CLK
CKE
BA0
CAS#
Vcc
CS#
RAS#
DQM0
DQM1
VccQ
RP#
DNU
Vss
WE#
DQ7
DQ5
DQ3
K
L
DQ8
VSSQ
VSS
DQ10
DQ12
VccQ
DQ15
DQ9
DQ14
DQ6
DQ1
VccQ
Vcc
VccQ
VccQ
DQ4
DQ2
M
N
P
VSSQ
DQ11
DQ13
V
SS
Q
VSSQ
Vss
DQ0
R
OPTIONS
• Configuration
MARKING
90-Ball FBGA – 4 Meg x 16
4 Meg x 16 (1 Meg x 16 x 4 banks)
2 Meg x 32 (512K x 32 x 4 banks)
4M16
2M32
1
2
3
7
8
9
DNU
DNU
V
SS
Vcc
DNU
DNU
A
B
C
D
E
• Read Timing (Cycle Time)
10ns (100 MHz) @ CL2
8ns (125 MHz) @ CL3
-8
-8
-10
DNU
VccQ
DNU
DNU
DNU
MCL
A5
V
SS
Q
VccQ
DNU
DNU
NC
VSS
Q
DNU
VccQ
VccQ
VssQ
Vcc
V
V
SS
Q
Q
DNU
DNU
NC
DNU
DNU
DNU
MCL
A0
10ns (100 MHz) @ CL3
SS
• Package
VccQ
90-ball FBGA
FG
VSS
A3
A2
F
A4
A7
A6
A10
NC
A1
G
H
J
Part Number Example:
MT28S4M16B1LLFG-8
A8
VccP
A11
A9
BA1
CS#
NC
CLK
CKE
BA0
CAS#
Vcc
RAS#
DQM0
KEYTIMINGPARAMETERS
DQM1
VccQ
RP#
WE#
DQ7
DQ5
DQ3
K
L
DQ8
DQ10
DQ12
VccQ
DQ15
Vss
VSSQ
ACCESS
SPEED
CLOCK
TIME
SETUP HOLD
VSS
DQ9
DQ14
DQ6
DQ1
VccQ
Vcc
VccQ
VccQ
DQ4
DQ2
M
N
P
GRADE FREQUENCY CL = 1* CL = 2* CL = 3* TIME TIME
VSSQ
-8
-10
-8
125 MHz
100 MHz
100 MHz
-
-
-
-
-
7ns
7ns
-
2ns
2ns
2ns
1ns
1ns
1ns
DQ11
DQ13
V
SS
Q
VSSQ
Vss
DQ0
R
8ns
NOTE: 1. The # symbol indicates signal is active LOW.
* CL = CAS (READ) Latency
64Mb: x16, x32 SyncFlash
MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02
©2002,MicronTechnology,Inc.
1
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRONWITHOUTNOTICE.PRODUCTSAREONLYWARRANTEDBYMICRONTOMEETMICRON’SPRODUCTIONDATASHEETSPECIFICATIONS.