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MT28S4M16LC PDF预览

MT28S4M16LC

更新时间： 2022-12-11 18:17:59
品牌 Logo 应用领域
镁光 - MICRON /
页数 文件大小 规格书
48页 987K
描述
SYNCFLASH MEMORY

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MT28S4M16LC 数据手册

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4 MEG x 16  
SYNCFLASH MEMORY  
SYNCFLASH®  
MEMORY  
MT28S4M16LC  
1 Meg x 16 x 4 banks  
FEATURES  
• 100 MHz SDRAM-compatible read timing  
• Fully synchronous; all signals registered on  
positive edge of system clock  
PINASSIGNMENT(TopView)  
54-PinTSOPII  
• Internal pipelined operation; column address can  
be changed every clock cycle  
• Internal banks for hiding row access  
• Programmable burst lengths: 1, 2, 4, 8, or full page  
(READ)  
• LVTTL-compatible inputs and outputs  
• Single +3.3V ±0.3V power supply  
– Additional VHH hardware protect mode (RP#)  
• Four-bank architecture supports true concurrent  
operations with zero latency:  
V
DQ0  
CC  
1
2
3
4
5
6
7
8
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
DQ15  
VSSQ  
DQ14  
DQ13  
VCCQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
VCCQ  
DQ8  
VSS  
RP#  
DQMH  
CLK  
CKE  
V
CC  
Q
DQ1  
DQ2  
V
SS  
Q
DQ3  
DQ4  
V
CC  
Q
9
DQ5  
DQ6  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
V
SS  
Q
DQ7  
V
CC  
Read from any bank while performing a  
PROGRAM or ERASE operation to any other  
bank  
DQML  
WE#  
CAS#  
RAS#  
CS#  
BA0  
BA1  
A10  
A0  
A1  
A2  
A3  
V
• Deep power-down mode: 300µA maximum  
• Cross-compatible Flash memory command set  
• Industry-standard, SDRAM-compatible pinouts  
– Pins 36 and 40 are no connects for SDRAM  
VCCP  
A11  
A9  
A8  
A7  
A6  
A5  
A4  
OPTIONS  
• Configuration  
MARKING  
CC  
VSS  
4 Meg x 16 (1 Meg x 16 x 4 banks)  
4M16  
NOTE: The # symbol indicates signal is active LOW.  
• Read Timing (Cycle Time)  
10ns (100 MHz)  
-10  
-12  
12ns (83 MHz)  
KEYTIMINGPARAMETERS  
• Package  
54-pin OCPL1 TSOP II (400 mil)  
TG  
SPEED  
CLOCK  
ACCESSTIME  
SETUP  
HOLD  
TIME  
GRADE FREQUENCY CL = 2* CL = 3* TIME  
• Operating Temperature Range  
-10  
-10  
-12  
-12  
100MHz  
66 MHz  
83 MHz  
66 MHz  
–
9ns  
–
7ns  
–
9ns  
–
3ns  
3ns  
3ns  
3ns  
2ns  
2ns  
2ns  
2ns  
Commercial Temperature (0ºC to +70ºC) None  
NOTE: 1. Off-centerpartingline  
10ns  
Part Number Example:  
MT28S4M16LCTG-10  
*CL = CAS (READ) latency  
GENERALDESCRIPTION  
This SyncFlash® data sheet is divided into two ma-  
jor sections. The SDRAM Interface Functional  
Description details compatibility with the SDRAM  
memory, and the Flash Memory Functional Descrip-  
tion specifies the symmetrical-sectored flash architec-  
ture functional commands.  
The MT28S4M16LC is a nonvolatile, electrically sec-  
tor-erasable (Flash), programmable memory contain-  
ing 67,108,864 bits organized as 4,194,304 words (16  
bits). SyncFlash memory is ideal for 3.3V-only plat-  
forms that require both hardware and software protec-  
tion modes. Additional hardware protection modes are  
4 Meg x 16 SyncFlash  
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01  
©2001,MicronTechnology,Inc.  
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.  
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